Jonathan Hauke Email & Phone Number

Santa Clara, California, Us

Santa Clara, California, Us

Power owner for AMD’s semi-custom business unit.- Led and managed a team of engineers to deliver power commitments across multiple projects and customers- Responsible for customer communication on all power topics- Implemented improvements on AMD’s power modeling and correlation flows used by all semi-custom projectsPower architecture- Delivered on semi-custom goal to bring the SCBU power organization in-line with the rest of AMD’s client and dGPU methodologies and flows- Led initiatives to implement power savings features in SCBU products before they were available across AMD’s standard product portfolioPower modeling- Responsible for creating and maintaining accurate power models across multiple products and multiple generations of technology and architecture- Worked directly with customers, internal design teams, and foundry to ensure high quality results- Integrated data from platform and product engineering in order to refine and tighten model parametersPower management- Owned the system-level power management architecture for a custom microprocessor.- Developed new power management flows to meet SOC specifications.- Worked with IP units to utilize and engage power management functionality in individual blocks.- Wrote and maintained technical specifications to document old and new power management flows.- Collaborated with cross-site verification and platform validation teams to ensure functionality was properly tested and covered in order to minimize post-silicon debug efforts.- Submitted patent applications and worked with patent lawyers to protect new technology and flows.

Santa Clara, California, Us

7 years of experience designing x86 mobile microprocessors.- Concept to completion microarchitecture, design, debug, and collaboration for various microprocessor components, such as: - Designed power management hardware necessary to control chip-wide power via the Client Northbridge, including coordination for multi-core and multi-threading hardware. This hardware was productized in AMDs first generation of Fusion APUs. - Received 2 patents (see “Patent” section) for power management related designs. - Pieces of the Load-Store Unit, including bypass interfaces to the physical register file, and resizing caches to fit new designs. - Debugged global processor issues and worked closely with the Verification team to ensure adequate testing and coverage in order to verify my logic.- Managed full-chip connections between various IP sources to ensure 100% top-level connectivity for a next-generation mobile processor.- Designed complex spreadsheet and database tracking systems used for analyzing and coordinating various processor features across multiple SOCs.- Served as a technical writer for both system and IP level power management flows for the “Trinity” APU. Delivered documentation that was visible by BIOS and validation teams, in addition to external customers

Armonk, New York, Ny, Us

Designed a network ASIC for the BlueGene/P supercomputer, from project definition through completion.- Assisted in creating the high-level architectural definition for the ASIC.- Completed design and debug of the parity unit, which comprised the majority of the logic on the chip.- Delivered full synthesis model of the chip, and was responsible for all synthesis-related tasks.- Analyzed and fixed timing related issues in logic throughout the ASIC.- Interacted with both the Verification and Physical Design teams to ensure timely delivery of the ASIC.- Mentored a new-hire and served as his “Connection Coach” for integrating him into IBM.

Palo Alto, Ca, Us

5 years of experience working on and leading parts of a next-generation Ultra Sparc microprocessor.- Concept to completion design, debug, and collaboration of key components of the processor microarchitecture, such as: - Substantial portions of the Instruction Renamer in Verilog, including the handling of register windows, pipeline flow control, and instruction dependency detection. - Major portions of the Instruction Fetcher, including the logic to handle thread-switching transitions in hardware, the interrupt and trap flow mechanisms, and special purpose registers.- Undertook RTL leadership of a major block (Renamer) mid-project, and successfully delivered all milestones until tapeout.- Worked with the Verification team to ensure that coverage matrices, testing, and formal tools were used properly to adequately verify my blocks.- Collaborated with the Circuit Design team to solve critical timing paths and guide portions of the design through the back-end flows.

Msce, Computer Engineering

Bsee, Electrical Engineering