Kevin Grosselfinger Email & Phone Number

Williston, Vt, Us

Burlington, Vermont

I manage the ASIC Design Group for ASIC North. We are a microelectronic design service company with design centers in Burlington VT, Tempe AZ, and Raleigh NC.

Burlington, Vermont Area

- Managed a team of 16 engineers, across four different locations, responsible for the design and life cycle qualification of semiconductor packaging programs for Server, Games, and ASIC product segments.- Responsible for appraisals, compensation planning, and career development for the team.- Received the System &Technology Group’s “Top 50 People Manager” award in 2007 for excellence in people management. Nominated as result of input from employees and upper level management.- Led the financial planning process for a $65M packaging development budget. Presented to executive management on roadmap, ROI, and priority analysis for the 140-person packaging organization

Burlington, Vermont Area

- Technical staff assignment reporting to the director of IBM packaging development, charged with improving the design processes of silicon packaging; meeting time to market, electrical integrity, and quality goals.- Led the negotiation and implementation of contracts with external vendors on the development of package design tools. Coordinated with legal council, procurement, and business development organizations on the finalization of contracts. Developed benchmarking methods to measure success of the contracted deliverables.- Headed a thirty-five member cross-functional team consisting of silicon designers, package designers, and design automation engineers on a chip/package co-design process. Measured success of these projects through customer serviceability, throughput, and the quality of designs.

Burlington, Vermont Area

Integral member of the advanced products team. Responsible for the technical definition of a 90nm silicon process family for the IBM ASIC business. Coordinated the design and implementation of early test sites targeted for technology and design system bring-up. Worked with manufacturing development and technical marketing to match customer expectations with the initial product offerings.- Granted two US Patent Awards for novel approaches to low power circuit design techniques including active power reductions, transistor well biasing techniques, and on-chip power control switches.- Led a team of ten people to improve the quality of models used in the physical design of integrated circuit products by implementing an automated model generation tool with a web interface and database infrastructure.

Burlington, Vermont Area

- Responsible for the design of a highspeed memory interface into 4 different ASIC technology families. Collaborated with an Intellectual Property (IP) supplier on design of mixed signal circuits and issues migrating designs for next generation silicon processes.- Worked closely with customers on system level integration of the memory interface. Entailed simulation and logic integration, physical design, system bring-up, package, and board level constraint management. Included multiple on-site customer visits.- Developed a ‘turn key’ physical design system that incorporated the memory interface into the wide array of chip options as part of an ASIC offering. Included matching performance needs of the system interface with physical design limitations of the silicon environment.- Led, designed, implemented, characterized, and qualified four test sites implementing the memory interface in IBM’s ASIC technologies.

Masters, Electrical Engineering

Bachelors, Electrical Engineering

Education record