Bob Lynch Email & Phone Number

RTP, NC

Wrote timing assertions for cores. Ran and closed core timings at core level. Worked with chip-level timing designers to create timing contracts and rules for cores. Identified and fixed electrical violations inside cores (EM, noise, slew violations). Optimized core-designs for power-reduction.- Improved accuracy by serving as timing lead on HSS 22 and.

Served as Technical Project Manager, supervising the adding of analog-IP designs into IBM's ASIC library (65-130nm nodes). Handled rule generation, front / back-end checking, documentation, test-site / qualification support.- Recognized for successfully verifying and incorporating designs into ASIC library, which included: - 3G HSS core from ARM. - XIO.

Created platform-based designs based on IBM’s CoreConnect bus architecture and PowerPC 405/440 processors.- Performed core-stitching, chip-level design, timing, verification and customer support, resulting in 4XX PBDs being included in all IBM ASIC library offerings, serving as starting points for customer ASSPs.

Served as lead circuit designer on first PowerPC 405 core. Co-developed low-power library with IBM ASICs. Served as technical lead on 405 remap and member of 5-person team on 405 core for Xilinx FPGA. Oversaw rule creation and release of PowerPC 464 design (90 nm node).- Recognized by corporate award for technical achievement on PowerPC 405 core design..

SP (SUPER PARALLEL) COMPUTER DESIGNServed as back-end designer for SP ADAPTER CHIPs. Oversaw clocking, self-test, placement, and timing of RS6000-SP adapter / switch chips. Chips contained custom-designed self-timed interface logic running at 500 MHz.- Recognized for work by chips used in Blue-Gene design, which was awarded National Medal of Technology in.

Worked in various positions in mainframe S390 area. Served as circuit design team lead for I-unit S396 CMOS chip, circuit team lead on bipolar embedded ram macros for air-cooled mainframes and TCM / Trace designer on air-cooled mainframes.- Received corporate award on air-cooled mainframe for increasing system performance 30%.- Achieved 1 issued patent for.

Served as lead PD engineer on uP core for IBM token Ring Adapter chip (first IBM chip to incorporate Analog / Digital functions on same chip). Served as lead circuit designer for random logic library used on PC COAX Adapter chip (3270 terminal emulation on a PC) and circuit designer of register array file and custom alu for 24bit uP controller chip..

Designer of 64X8 static Ram macro and ELECTRICALLY ALTERABLE PLA in NMOS technology.

Msee, Electrical Engineering

Bsee, Electrical Engineering