Harini N Email & Phone Number

Bangalore

Implementation of Physical Design flow( Netlist to GDS) on few critical blocks which are operating at 1.5GHz Frequency .Technology Used is 14nm .Using Global Foundries deliverables for Low Power execution.Implementation tools from Synopsys: ICC2 for complete physical Design implementation,StarRC for Extraction, Prime Time for Timing sign off ,Calibre for Physical Verification.Client: Advanced Micro Devices (AMD)

Bengaluru Area, India

I have implemented block level designs from netlist to GDS under 65nm,40nm,28nm and 14nm technology nodes with multiple clients.Basically some part of sign off (i.e Physical verification,Prime Time and IR analysis is implemented on TopLevel designs as well.I am familiar with Cadence Encounter ,ICC and Magma tools with respect to physical design Implementation.Regarding sign off I have used Calibre ,PrimeTime ,EPS and redhawk tools.

Santa Clara , California

My role was block Level Implementation in physical Design from Netlist to GDS,and performed sign off checks as well. Done with the implementation of ECO,s in the design.

Pune

Done M.Tech in VLSI.

Masters, Vlsi

As a Student,I was the member of placement committe. I used to prepare Interviw questions and conducted Written tests.

B.Tech, Electronics

I have done my Graduation in Electronics and Communication Engineering. Presented and Published few papers at state level.