Harish Gopalakrishnan

Harish Gopalakrishnan Email and Phone Number

Sr. Prinicipal Engineer @ Analog Devices
Bengaluru, KA, IN
Harish Gopalakrishnan's Location
Bengaluru, Karnataka, India, India
About Harish Gopalakrishnan

With over a decade of experience in the semiconductor industry, my expertise lies in SoC power optimization and hardware architecture, and I am currently leading the SoC Power team at Intel Corporation. At the heart of my professional drive is the pursuit of innovation in power-efficient designs that align with Intel's commitment to leading-edge technology. My role allows me to contribute diverse perspectives and rigorous methodologies that reinforce Intel's mission and culture.Since joining Intel in June 2022, my focus has been on the IPU ASIC within the Agliex product line, where I utilize my significant skills in Linux and power optimization. The role encompasses overseeing the power sign-off from architecture definition to post-silicon validation, ensuring that our customer samples meet the highest standards of efficiency and performance. Our team's collaborative efforts continue to enhance Intel's market leadership in power-efficient computing solutions.

Harish Gopalakrishnan's Current Company Details
Analog Devices

Analog Devices

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Sr. Prinicipal Engineer
Bengaluru, KA, IN
Website:
analog.com
Employees:
25472
Harish Gopalakrishnan Work Experience Details
  • Analog Devices
    Sr. Prinicipal Engineer
    Analog Devices
    Bengaluru, Ka, In
  • Intel Corporation
    Soc Power Lead
    Intel Corporation Mar 2021 - Present
    Bangalore Urban, Karnataka, India
    SOC Power Lead for IPU ASIC - Intel's Agliex product line
  • Qualcomm
    Senior Staff Engineer
    Qualcomm Sep 2016 - Mar 2021
    Chennai Area, India
    - SoC Power Lead for Qualcomm Snapdragon, Modem, and IoT product line- Experience working on Ultra-Low-Power architecture for 28nm, 14nm, 12nm, 7nm- Handled Power Sign-off from SoC power architecture definition to Post Silicon validation for customer samples- Responsible for RTL, Netlist CLP Sign-off, Power Budgets, Estimation & Optimization, support PDN power analysis and sign-off- Contributed to developing and mentoring a new team for Soc Power Sign-off (defining new flows, processes & methodolgy along with technical guidance)
  • Intel Corporation
    Senior Graphics Hardware Engineer
    Intel Corporation May 2012 - Aug 2016
    Bengaluru Area, India
  • Intel Corporation
    Graphics Hardware Engineer
    Intel Corporation May 2009 - May 2012
    Folsom, California
    - Design Methodology, Tool flows, SoC Integration owner for Graphics SIP - worked closely with RTL design team & physical design team on floorplan optimization, routing, and timing fixes- Internal Design library management - reduce verification time, reuse of common IP to minimize bug rate, parameterization of IP for scalability- Design and microarchitecture development for Image Enhancement Hardware acceleration engine - Denoise, Deinterlacer, Demosaicing- IP Test plan development, Verification, Performace verification, Synthesis, timing fixes, Data pipeline optimization for gate count reduction- Actively engaged with multiple horizontal teams - Algorithm development team, Architecture, Physical design, Power verification, FPGA validation, Post Silicon Functional & Performance validation
  • Intel Corporation
    Component Design Engineer
    Intel Corporation May 2005 - May 2009
    Folsom, California
    - Power Estimation, Modelling, and Optimization : Thermal Design Power (TDP) estimation for 3D Graphics core, Leakage power optimization, Clock power analysis and optimization- Build a Power Model for the Internal Graphics Soft IP core based on the industry benchmarks- Signal integrity checks, IR droop analysis, identify hot spots based on TDP workloads and define bump placements- DDR II and Display power managment testplan definition and vector development

Harish Gopalakrishnan Education Details

Frequently Asked Questions about Harish Gopalakrishnan

What company does Harish Gopalakrishnan work for?

Harish Gopalakrishnan works for Analog Devices

What is Harish Gopalakrishnan's role at the current company?

Harish Gopalakrishnan's current role is Sr. Prinicipal Engineer.

What schools did Harish Gopalakrishnan attend?

Harish Gopalakrishnan attended Oregon State University, Sathyabama University.

Who are Harish Gopalakrishnan's colleagues?

Harish Gopalakrishnan's colleagues are Mike Stowe, Peter Cuddihy, 张娅丹, Steve Pietkiewicz, Adam Seal, Hao Zhang, Christopher Orense.

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