Hassan Harb Email and Phone Number
Wealth of experience in the area of Product and Test development on a broad mix of System-on-Chip products, ranging from low pin count ASIC to a very large pin count complex networking devices. Product portfolio includes ASIC, MCUs (8/16/32/64-bit), Sensors, MEMS, Motor Control, DSP, USB, Wireless, RF, Set-Top box, Network, Multi-Media, Discrete Small Signal & Protection, eFuse, Logic, and Memory products. Driving cost effective and high growth margin NPD qualified to multi-market requirements (Commercial, Industrial, Automotive, and Military applications, QS9xxx, AEC, and Mil-8xx). . Manging a group of NPD Project Leaders for Logic and Memory products (from Feasibility to RTM).. Managed a group of NPD Project Leaders for eFuse products. (from Feasibility to RTM).. Coordinated cost reduction activities in Fab, Assembly, Test and Manufacturing. (results: >$12M ann). . Designated MMTS, recognized for advanced knowledge and technical leadership capabilities.· Lead yield Improvements at probe, assembly and final test (results: cumm yield >97%).· Set priorities, assign resources and manage milestones across groups. · Co-ordinated training of new product releases to offshore sites. · Lead teams, thru influence, w/strong ability to deliver on commitments. Strong communication skills. . Strong knowledge of P&L. Good track record of Operational and Manufacturing Excellence.· Consistent effectiveness and outstanding project results. Possess technical acumen in all areas of product and test. Proven problem solving track record. Possess strong knowledge of global markets. Skills in new products launch. Dedicated to lead and complete programs by inspiring subordinates and successfully lineup resources and needed support. Capable of setting up effective group goals and priorities. Capable of handling competitive situations with confidence and tact.Specialties: Engineering Management position in the area of Product & Test or Quality or Program Management/Project. Expertise in New Product Introduction (NPI) from inception phase into high volume production of semiconductor system-on-chip solution with mixed analog and digital technology.
Microchip Technology Inc.
View- Website:
- microchip.com
- Employees:
- 12481
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Npd Technical Project ManagerMicrochip Technology Inc. Jan 2022 - PresentChandler, Az.
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New Product Development (Npd), Managing Technical Team Of Project Leaders (From Feasibility To Rtm)On Semiconductor Jul 2013 - Dec 2021Phoenix, AzIntegrated Circuits and Protection/Small Signal Division (ICPSD): Jul 2013 to Dec, 2021. . Managed a group of NPD Project Leaders for Logic and Memory products (from Feasibility to RTM).. Managed a group of NPD Project Leaders for eFuse products. (from Feasibility to RTM).. Managed a global engineering team for implementing and monitoring major cost reduction activities in various manufacturing sites. Cost reduction activities in wafer fab, assembly, and final test. Achieved $12 Million Dollars of cost savings annually for 4 consecutive years.. Lead strategic cost reduction activities including design shrinks (MBAV99), process improvements (Au-Pt thickness), assembly (top 6 cost offenders), test yields (97%), and manufacturing flows (optimization) to increase gross margins, profits and maintain competitive market share position. . Managed a local product engineering team (NPD) and provided technical support to resolve manufacturing issue (Issues mandated by major customers: Quality Incidents reduction (EFARs), Customers returns (Test escapes, loose limits, etc...). Managed and Hands-on several new products development: wireless bridge rectifiers for charging devices and LED lighting controls. -
Sr. Product And Test Engineering Manager Sasd / Npi Product Manager Nmg-Npd / Sr. Manager PntFreescale Semiconductor Jul 2008 - Dec 2012Freescale Semiconductor July 2008 To Dec 2012 Tempe, Az / Austin, Tx / Chandler,Sr. Product and Test Engineering Manager SASD / NPI Product Manager NMG-NPD / Sr. Manager Product & Test NMG-DHO· Designated Managing Member of Technical Staff (MMTS). Recognized for advanced knowledge and technical leadership capabilities.· Drive Gross Margin improvements thru Cost Reduction activities focusing on top revenue Auto and C&I products. Focused activities on Yield Improvements at probe, assembly, final test. · Manage a global product & test sustaining team for Auto & C&I Sensors products. · Manage MEMS engineering labs (equipments and personnel) to support product testing for customer samples, qualification samples, DOE’s, CQI’s, and FA samples. · Responsible for New Product Introduction (NPI-DHO) and sustaining of high volume products in production.· Develop competitive products (DHO) in three major market areas: RF, Set-top boxes and Networking. · Perform new silicon evaluation, characterization and qualifications to Industrial and Automotive markets. · Perform die and package qualifications for both internal and external FAB, Assembly and Test sites.· Championed a Task Force Team to evaluate and recommend the next generation low cost tester platform for the Ultra Low End/Low Power Networking products. Resulted with major cost savings.· Achieved record number of new product releases (Qualification, Characterization, and release to production) in one single quarter. · End-of-life older, low volume, and low revenue products. Transfer high revenue products to internal and external manufacturing sites (FAB, Assembly, and Test). -
Director Of Engineering, Consumer & Computation Division (Ccd)Cypress Semiconductor Corp Sep 2006 - Jul 2008Lynnwood, Wa.• Responsible for the development of new PSoC products roadmap (8/32-bit Microcontrollers) and support of existing PSoC (8-bit), USB, Wireless USB, and RF products.• Performed silicon validation, characterization, qualification, and release to production.• Managed global product and test engineering groups (WA, India, Philippines). • Managed P&L for the global product and test groups. • Developed New Product Plans (NPP) and schedules, from design kick-off phase throughout high volume production phase, • Set targets/goals for profit improvements (low cost wafer sort, assembly and final test, high yields, and high quality indices (low PPM and DPM), excellent AOQ, and zero retest/rework).• Key contributor to increase market share in both automotive and commercial markets. -
Product & Test Engineering Department Manager, Digital Signal Controller Division (Dscd)Microchip Technology Inc Nov 2000 - Sep 2006Chandler, Az.• Established (staff and manage) the Product & Test Engineering Department for the new dsPIC Division. • Developed the new dsPIC products roadmap and supervised overall product plans and schedules.• Special focus on time-to-market products. • Managed all dsPIC NPI. The dsPIC products consist of Integrated DSP and CPU as the Core architecture with Analog and Digital peripherals. • Managed three engineering groups: Product & Test development, and Manufacturing support. • Developed roadmaps for low cost/low pin count and high profit margin products. • Developed plans for lower cost improvements at probe, assembly, Final test, and QA. • Developed Test program plans with built-in high quality tests using low cost testers. • Developed plans for test-case simulation and test pattern generation utilizing Automated Cadence Tools.• Performed new product/process evaluation, characterization, qualification, and release to production.• Performed specific NVM-Flash reliability testing. • Developed product & test engineering training plans and provided offshore training for sustaining group.
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Product Engr Management (Product, Test, Program, Ind. Contributer)Motorola Inc Jul 1992 - Nov 2000Austin, Tx. And Munich, Germany.Customer Focused Account Product Manager Jan 2000 to Nov 2000 Austin, TX• Provided Technical and Tactical resolutions for a major automotive customer.• Special focus - exceeding customer expectations: • Product performance, Quality, and On-time delivery. • Promoting latest technology SoC solutions. • Provide world-class product service at competitive pricing.Program Manager Feb 1998 to Dec 1999 Munich, Germany• Managed a global team (Design, Technology, Fab, Assembly, Product, Test, and Manufacturing). • Significant customer interaction - product definition & specs (HC12 based). • Contributed in high level customer meetings - future products• Market value pricing.• Project planning & delivery dates.• Defining next low cost tester platforms.• Provide SoC solutions for future automotive applications.Engr Scientist/Staff Principal and PE Manager July 1995 to Feb 1998 Austin, TX• Developed the HC11 product shrink roadmap. Lead the engineering efforts to qualify the first 68HC11E9 73% shrink product in MOS5 and fan it out to other Motorola Fabs.• Lead a cross-functional team to develop and qualify the Robust IDR process, which resulted in significant EEPROM endurance improvement (10X improvement) and also lead to the elimination of Burn-In.Staff PE/PE Lead July 1993 to July 1995 Austin, TX• HC11 product introduction. Lead a small team of product engineers to develop test programs and test patterns, provided customer samples, qualified and released products to production (local and offshore).• Introduced cost reduction processes (No Retest of Rejects, Multi-DUT testing) on Advantest T33XX testers.Staff PE July 1992 to July 1993 Austin, TX• Responsible for probe and final test hardware design.• Developed Test programs for several HC11 products.• Performed HC11 products (50% and 60% shrink) qualification and release to production.• Transferred HC11 products to offshore test facilities. -
Principal Engineer/Team LeaderNational Semiconductor Corp Oct 1988 - Jul 1992West Jordan, Ut.• Designed HW and developed test SW for wafer probe on Teradyne A300 mixed signal testers.• Analyzed electrical test data collected from process monitoring wafers.• Designed experiments to evaluate process shifts and its impact on product yield and performance.• Designed wafer process targets (Critical dimensions, Alignment keys, Vernier) for process monitoring.• Verified layout plots of all incoming Analog products.• Implemented Inspection procedures for incoming masks/reticles to ensure good probe yield. -
Senior Product-Test Engineer / Team LeaderIntel Sep 1987 - Sep 1988Chandler, Az.• Responsible for the 80C451 Product and Test development.• Designed hardware and developed test software for 80C451 probe and final test on Teradyne J941 testers.• Performed cold test elimination experiments.• Qualified and released to production (local and offshore) existing 80C51 product derivatives.• Performed product characterization and tester-to-tester correlation.• Conducted root cause analysis on low yielding material (wafers and parts). -
Test Development EngineerAmerican Microsystems Inc Jun 1984 - Sep 1987Pocatello, Id.• Developed Test program for mixed signal products (CMOS DAC, Medical, Telecom and Disk Drive IC’s).• Designed probe and final test HW and SW on Teradyne A300, and Sentry VII and XXI testers.• Generated test patterns from simulation phase to tester platform.• Performed product test evaluation, characterization, qualification, and released quality TP’s to production.
Hassan Harb Education Details
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University Of PhoenixBusiness Management -
Utah State UniversityElectrical Engineering, Physics Minor
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Electrical Engineering
Frequently Asked Questions about Hassan Harb
What company does Hassan Harb work for?
Hassan Harb works for Microchip Technology Inc.
What is Hassan Harb's role at the current company?
Hassan Harb's current role is NPI Technical Project Manager at Microchip Technology Inc..
What schools did Hassan Harb attend?
Hassan Harb attended University Of Phoenix, Utah State University, Utah State University.
Who are Hassan Harb's colleagues?
Hassan Harb's colleagues are Florina Rasoi, Mary O'shea, Romelle Gonzales, Prabhu D., Ge Lo, Sathish T.s, Aruna Konakanchi.
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Hassan Harb
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