1. In my seventh project, I was responsible for the physical design (PD) implementation of a block. Additionally, I conducted flow flush experiments and trials to identify the most effective methodology for PD implementation. To enhance IR, I developed a script that aggressively adds vias to violating instances while being DRC aware, capable of processing thousands of instances in minutes. I also contributed to setting up the flow for smaller digital designs, identifying and resolving issues to ensure optimal workflow for the rest of the designs in the project.

1. In my first project with the Physical Design team, I implemented two blocks for an automotive PHY SOC. This role involved tackling memory and analog challenges, managing analog interfaces, and applying timing fixes via clock skew manipulation on source synchronous buses. Additionally, I developed skills in cleaning up DRCs and achieving PV closure. 2. In my second project, I was responsible for the top-level physical design (PD) implementation for an IP, working collaboratively with the team to integrate multiple sub-blocks. This role significantly deepened my expertise in hierarchical PD implementations. I navigated complex challenges, including trimming the existing power grid and placing a new instance without a respin. Additionally, I conducted flat timing, physical verification (PV), power grid verification (PGV), and PERC runs for the first time.3. In my third project, I contributed to a connectivity SoC operating at higher frequencies in advanced technology nodes. I was responsible for the physical design implementation of a complex block, which included an Analog IP and a high-frequency module. One of the key challenges was closing the timing of the high-frequency module, for which I successfully utilized an H-tree for clock distribution, significantly reducing skew.4. Simultaneously, while handling the above project, I also managed an automotive SoC for chip-level ECO implementation. This metal-only tapeout presented timing/DRV challenges, as I had to route multiple nets with pins spaced 1200 µm apart. Unable to modify the base layer, I repurposed spare cells into buffers and scripted the process to expedite turnaround in a highly congested channel.5. Following these projects, I worked on two consecutive projects that underwent ECO cycles with a tight tapeout schedule. I efficiently addressed issues and developed solutions to ensure the blocks under my responsibility were signoff-ready within the limited timeframe.

During my internship at Marvell as part of the Master’s program, I conducted in-depth research on advanced technology nodes to analyze cell-interconnect timing delay characteristics under various conditions. This work resulted in the creation of a comprehensive database, significantly improving the accuracy and efficiency of PD engineers’ timing adjustments. Additionally, my preliminary studies on characterizing electromigration (EM) violations provided valuable insights on enhancing the reliability of advanced designs.Leveraging this experience, I submitted my thesis titled “Implementation of Custom Digital Design Framework for Analysis of Library Cell & Interconnect Timing and EM Characteristics in Advanced Technology Node.” This research has significant industry implications, providing valuable methodologies for enhancing the precision and reliability of timing and electromigration analysis in cutting-edge semiconductor technologies.

In my role as a Graduate Teaching Assistant at MIT, Manipal, I played a key role in the development of a comprehensive lab manual for the B.Tech 6th semester, a project that spanned three months. This involved meticulous research, content creation, and collaboration with faculty members to ensure the manual met academic standards. Subsequently, I transitioned to the role of Teaching Faculty Assistant in the same lab for the following semester, where I was responsible for assisting in lab sessions, guiding students through experiments, and providing academic support to enhance their learning experience.