Aamir Husain Email & Phone Number

Burnaby, Bc, Ca

Burnaby, Bc, Ca

Burnaby, British Columbia, Canada

Burnaby

Burnaby, Bc

Radisys MEBU develops carrier class IP media servers used by network operators and solution providers.Provided technical support/guidance to customer support, product line marketing and field engineers. Worked on proof of concept design for solutions to various problems.Monetized new revenues by supporting the migration of value added services for mobile video for broadband LTE IMS deployment using the next generation MPX12000 product line by:• Developing the high level software design specifications for the DSP sub-system and key contributor in high level architectural design of the Intel based MPC5 and TI based MPC6 media processing card with multi-core chips. • Designing, implementing, optimizing, testing the complete porting of the MRF feature set to the new MPC cards.• Working with other teams and board/chip vendors to resolve platform/system level issues.Defined high level design to reduce the packetization interval to 5ms from 10ms in delay sensitive applications. Integrated EVRCB codec and implemented a noise reduction solution as part of voice quality enhancements.Defined requirements and researched, designed, implemented and tested an efficient acoustic echo cancellation system for VoIP networks. This feature addition resulted in tens of million dollars in additional revenues (hardware and licensing sales) which resulted in significant company profits for several years.Led DSP development by providing continuous presence video conferencing feature on the product line by designing, implementing, optimizing, testing, and resolving issues in the DSP code to support video mixing, scaling and third party H263 video codec.Achieved wideband G.722 and H264 voice activated switching conferencing capability by leading DSP development through design, development and testing phases.Enabled migration to newer generation product line by architecting, designing, implementing and optimizing the DSP code to port from the c62x to the c64x TI DSP platform.

Burnaby, B.C

• Reduced prototype processor chip size and cost through development of VoP applications by designing, documenting, implementing and optimizing the G.726 speech coder and line echo canceller in C/assembler.• Enabled timely development of a prototype processor chip by performing verification and validation of the various processor units as well as integration level testing of the chip through designing and implementing code in C, Tcl/TK and assembler.• Completed on-time feasibility study of VoP proof of concept simulator system by designing and implementing in Tcl/TK, C and assembler, a task scheduling prioritizing algorithm that ran on a task controller unit as well as VoP applications and framework that ran on clustered processing units.• Collaborated in producing a white paper on multi-user detection in a WCDMA base-station using parallel DSP technology based on a high density baseband receive processor building block by researching WCDMA implementation issues and designing preliminary WCDMA baseband system blocks such as Rake receiver, channel estimation, path searching, descrambling, despreading and symbol processing. Produced an architectural hardware solution for symbol processing within a WCDMA base-station by researching and designing key symbol processing tasks and undertaking partial implementation of key blocks in C, Matlab and assembler.• Achieved customer processing and latency requirements for a possible solution to joint detection in a baseband receiver within a TD-SCDMA wireless base-station by: Collaborating in producing an architectural hardware chip solution to the joint detection problem and in developing its associated algorithmic data flow; Designing, documenting and implementing joint detection algorithm code in C and assembler; Assisting in development and verification of a cycle-accurate simulator of a single processor unit.

Burnaby Bc

Reduced cost and time to market by expediting the development of a DSP based wireless modem reference design for telemetry applications through designing, documenting, and implementing a host modem interface module ahead of schedule.Enabled timely development of a DSP based wireless modem in a keyboard-messaging device by redesigning, documenting and implementing the battery measurement driver module and assisting RF engineers in troubleshooting performance degradation in RF and baseband hardware.Accelerated milestone payment from customer by meeting deadline of designing, implementing and integrating an interface module on a DSP based location development device and improved the development of a network assisted GPS location device by providing assistance to system verification engineers towards achieving system wide verification of the location development device.Enabled penetration into new product space and acquired extensive knowledge of speech compression standards/systems by creating, designing & developing a high-quality, low-complexity, 1200 bps speech coder. Published one conference paper.Significantly improved performance and reliability of the 1200 bps speech coder and the speech recognition module of the Glenayre modular voice processing system by designing and developing a flexible and efficient front-end background noise suppressor.Instrumental in the timely deployment of the NPCS voice paging system by reducing costs significantly in amplitude modulated paging transmitters by researching, designing and developing a peak-to-average ratio compression technique for use in an NPCS voice paging system. Improved the performance of the NPCS voice paging system by performing system wide analysis, calibration and testing to optimize the design and increased message throughput by optimizing and implementing a silence elimination algorithm as well as timely delivery of the speech compression fixed-point algorithm used in the paging switch.

Burnaby, Bc

Developed efficient techniques, in CELP based speech coders, to reconstruct lost packet speech information at the receiver and developed a low-delay 8 kb/s vector excitation coder for use in a network environment. Published one book paper and four conference papers based on technology developed.

Phd, Engineering

Thesis: Speech Coding for Packetized Networks Developed efficient techniques, in CELP based speech coders, to reconstruct lost packet.

M.S, Electrical Engineering

B.Sc (Hons), Electronics And Electrical Engineering, First Class

Thesis: Simulation of a 16 kb/s candidate speech coder proposed for the European GSM standard