Project: PCI-e SSD• Analog IP library maintenance• SOC PCB evaluation board development• Use Python programming to estimate SOC power and area• Floor planning• IO pads assignment• Generate SOC datasheet and test plan• ADC 12-bit SAR with digital calibration• Low Power Bandgap• Low Power Relaxation OscillatorManagement and Coordination of Analog IP with IP Providers• Non-volatile Flash Memory IO Co-development with Analog IP Providers in 28nm process• Review Analog IPs such as PLL, Temperature Sensor, Process Monitor, PCI-e PHY, and LPDDR/DDR PHY for SSD Controller Applications in 16nm and 12nm processes• Power Estimations for PCI-e Board PMIC Requirement• Work with GUC on package substrate design• Lead SSD hardware development• Work with CM for mass production

Project: PCI-e SSD• Random Number Generator in 28nm process• Ring Oscillator in 28nm process• Crystal Oscillator in 28nm processManagement and Coordination of Analog IP with IP Providers• Non-volatile Flash Memory IO Co-development with Analog IP Provider in 28nm process• Review Analog IPs such as PLL, Temperature Sensor, Process Monitor, PCI-e PHY, and LPDDR/DDR PHY for SSD Controller Applications in 28nm process• Power Estimations for PCI-e Board PMIC Requirement

Project: HDD• 12-bit SAR ADC with digital calibration in 40nm process• Low Power Bandgap and PGA in 28nm processProject: SSD and EMMC• Low Power Oscillator, Low Power Bandgap, and Random Number Generator in 40nm process• NVIO design in 40nm process

Project: Ultra-Wide Band Transceiver• 3GHz-10GHz with 500MHz BW TX chain on 0.13um and 0.18um processes• LO rejection calibration characterization; inductor characterization using ADS for PA and PLL LC tank VCO• Evaluated LP and WP effects on 65nm process for DAC and ADC blocks

Project: Analog IP Blocks Design• SAR ADC on 0.18um and 0.25um processes• Crystal Oscillator on 0.18um and 0.25um processes

Project: DPS7000 Silicon RF Tuner• Low power IF VGA with 30dB DR (16dB gain to 46dB gain at 30MHz to 60MHz)• Up to 60dB IM3 at 0.7Vpp• Linear in dB voltage control• LC tank calibration• On-chip inductor modeling

Project: SA3603 Cellular Band TDMA Receiver Chip• Dual Gain Mode with high gain mode of 17.5dB gain, -4dBm IIP3 and 1.5dB NF and low gain mode of 2dB gain, 3dBm and 11dB NF LNA• 0dBm Input/Output LO buffer designs• Full Chip RF and LO Isolation Design• Full Chip Characterization• Supported Evaluation Board DesignProject: SA9503 Dual Band CDMA Receiver Chip• LNA Design SupportProject: QUBIC3 Inductor Test Chip• Asitic Program and Layout• Responsible for initial report and test reportProject: SA2421 2.45GHz Wireless LAN Transceiver• Dual Gain Mode with high gain mode of 14dB gain, -3dBm IIP3 and 2.5dB NF and attenuation mode NF LNA Design• Full Chip Characterization• Supported Evaluation Board DesignProject: CDMA Transmitter Chip• Upconvertors for Cellular and PCS Bands and Characterization

Project: MCU Optical Interface Design and PLL VCO Design• Operational Amplifier Design for both PLL and MCU• VCO Design• HSPICE Verification• PLL Benchmark Testing• MCU ESD and Latch-up Testing