Designing a custom ASIC mapping matrix multiplication and FFT transforms to one systolic array by devising and implementing new data and control paths in Verilog for tapeout in 22nm process.

• Translated high-speed voltage level shifters from 130nm to 40nm SiGe BiCMOS by adjusting device sizes to match or exceed original performance in rise/fall times, propagation delay, and drive strength.• Designed test benches in Assembler to evaluate the performance of devices in new PDK, establishing device configurations for optimal power and timing operation• Simulated high bandwidth, high gain, multi-stage IC amplifier in Cadence Assembler to identify and resolve discrepancies in noise, bandwidth, and gain between simulation and bench results for Mixed Signal IC