Jared Buckner
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Jared Buckner Email & Phone Number

Senior Engineer at NVIDIA
Location: Raleigh-Durham-Chapel Hill Area, United States 7 work roles 1 school
1 work email found @nvidia.com LinkedIn matched
✓ Verified August 2026 4 data sources Profile completeness 100%

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Work email j****@nvidia.com
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Current company
Role
Senior Engineer
Location
Raleigh-Durham-Chapel Hill Area, United States
Company size

Who is Jared Buckner? Overview

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Jared Buckner is listed as Senior Engineer at NVIDIA, a with 18356 employees, based in Raleigh-Durham-Chapel Hill Area, United States. AeroLeads shows a work email signal at nvidia.com and a matched LinkedIn profile for Jared Buckner.

Jared Buckner previously worked as Principal Engineer at Ampere and Senior Staff Engineer at Ampere. Jared Buckner holds Bs, Electrical And Electronics Engineering from Georgia Institute Of Technology.

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{first_initial}{last}@nvidia.com
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Profile bio

About Jared Buckner

Talented and innovative engineer and developer of semiconductor design software and methodologies with over 15 years experience in leading technology centers, including software used during the development and characterization of PowerPC and Snapdragon processor designs.

Listed skills include Embedded Systems, Debugging, Verilog, Soc, and 21 others.

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NVIDIA
Nvidia
Senior Engineer
santa clara, california, united states
Website
Employees
18356
AeroLeads page
7 roles

Jared Buckner work experience

A career timeline built from the work history available for this profile.

Senior Engineer

Current

Durham, North Carolina, United States

Feb 2020 - Present

Principal Engineer

Jun 2019 - Feb 2020

Senior Staff Engineer

Raleigh-Durham, North Carolina Area

Jul 2018 - Feb 2020

Senior Staff Electrical Engineer

Raleigh-Durham, North Carolina Area

Circuit Analysis Methodology* Created a SPICE macro language and supporting tool suite capable of generating complex SPICE stimulus and analysis test-benches.* Wrote perl and C++ parser and data-models for SPICE netlists, along with circuit elaboration, partitioning, and parameter evaluation.* Designed a tool to create custom SPICE cross-sections of large circuits by modifying extraction data. Tool uses an interactive TCL shell for configuration, and is used by advanced… Show more Circuit Analysis Methodology* Created a SPICE macro language and supporting tool suite capable of generating complex SPICE stimulus and analysis test-benches.* Wrote perl and C++ parser and data-models for SPICE netlists, along with circuit elaboration, partitioning, and parameter evaluation.* Designed a tool to create custom SPICE cross-sections of large circuits by modifying extraction data. Tool uses an interactive TCL shell for configuration, and is used by advanced designers as a platform for developing other tools.* Constructed models of on-chip variation suitable for selective derating of SPICE-measured delay paths using Monte Carlo simulation models.* Authored software to find sneak-paths and improper level-shifting between voltage domains. This caught design problems not covered by vendor tools before tape out.* Developed tool to create interconnect models from raphael table data, using a custom C++ implementation of Nelder-Mead Simplex minimization to determine model coefficients.* Created C++ libraries to manipulate and evaluate boolean logic expressions. Utilized this software to determine transistor stage logic expressions and validity conditions.Macro Characterization Methodology* Developed Qualcomm's NanoTime flow, automating io configuration, generation of characterization parameters, annotation of parasitics, and generation of reports and model views.* Developed tools for gathering SPICE-simulation results and constructing Liberty (.lib) data structures, including delay and constraint tables, capacitance, pulse-width, period, and power information.* Created command-line tools for querying, comparing, modifying, and merging Liberty files.Development and Data Quality Methodology* Created an auditing tool suite to check the correctness of macro deliverables and to manage releases.* Developed tools to manage and change between project-specific environments. Created installation scripts which ease new users adoption. Show less

Jan 2005 - Jun 2018

Electrical Engineer

Various

Somerset Design Center, Austin, Texas * Co-developed a new method to model and time footless domino logic within the STA framework. * Designed, developed, and fully documented a C++ API to Freescale's internal high-performance static timing analyzer * Enabling users to develop "pluggable"​ client programs for custom STA analysis, thus giving Freescale's timer a more global reach within the company. * Maintained, supported, and extended other aspects of Freescale's internal… Show more Somerset Design Center, Austin, Texas * Co-developed a new method to model and time footless domino logic within the STA framework. * Designed, developed, and fully documented a C++ API to Freescale's internal high-performance static timing analyzer * Enabling users to develop "pluggable"​ client programs for custom STA analysis, thus giving Freescale's timer a more global reach within the company. * Maintained, supported, and extended other aspects of Freescale's internal STA tool. * Analyzed performance and accuracy of timing models with respect to SPICE.StarCore Design Center, Atlanta, Georgia * Integrated digital design modules on DSP cores and analyzed resultant designs for timing and functional errors. * Synthesized, placed, and routed logic designs into manufactured digital IP. * Created verification software to automate the testing of Verilog design vs a software model of the DSP, with throughput enabled by a batch-based compute-farm-aware design. * Assisted with the integration of code-coverage tools into the internal verification. * Managed project-wide timing constraints and design data, including communicating with internal customers on design requirements and closure issues. * Captured design and analysis methodology with documentation, custom software, and makefiles. * Developed many tools that greatly reduced time between design iterations.Boynton Cellular Design Center, Boynton Beach, Florida * Designed and tested peripheral support circuitry for the baseband processor controlling a tri-band GSM phone. * Developed composite antenna patterns for cellular applications, including RF planning simulations, subscriber unit field patterns, and so forth. * Involved in the investigation of cellular RF propagation dynamics in multi-scattering environments. Show less

Sep 1999 - Jan 2005

It Support Technician

Atlanta, Georgia

* Performed general PC support for the School of Civil Engineering. * Installed and repaired computer software and hardware, including PC, Mac, and Unix computers and related peripherals. * Maintained approximately 300 computers school-wide. * Instructed students in the basic use of productivity and network applications, including Excel, Word, Netscape Navigator, and Adobe Acrobat.

Sep 1998 - Aug 1999

Electrical Engineering Intern

Norcross, Georgia

* Documented internal Operation of the 8600x cable set-top. * Organized transaction specification into an 80-page handbook used by software engineers to assist them during product development. * Assisted the development of a demonstration system for a national convention. * Successfully proposed a new automated testing system (ATS) to speed up the debugging process during alpha testing of set-top units. * Wrote Visual Basic 5 code for the Windows NT controllers as part of the… Show more * Documented internal Operation of the 8600x cable set-top. * Organized transaction specification into an 80-page handbook used by software engineers to assist them during product development. * Assisted the development of a demonstration system for a national convention. * Successfully proposed a new automated testing system (ATS) to speed up the debugging process during alpha testing of set-top units. * Wrote Visual Basic 5 code for the Windows NT controllers as part of the team effort to develop the ATS. * Wrote a C code implementation of Huffman compression to compress common text strings in the 8600x. Show less

Jun 1995 - Sep 1998
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Colleagues at NVIDIA

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1 education record

Jared Buckner education

FAQ

Frequently asked questions about Jared Buckner

Quick answers generated from the profile data available on this page.

What company does Jared Buckner work for?

Jared Buckner works for NVIDIA.

What is Jared Buckner's role at NVIDIA?

Jared Buckner is listed as Senior Engineer at NVIDIA.

What is Jared Buckner's email address?

AeroLeads has found 1 work email signal at @nvidia.com for Jared Buckner at NVIDIA.

Where is Jared Buckner based?

Jared Buckner is based in Raleigh-Durham-Chapel Hill Area, United States while working with NVIDIA.

What companies has Jared Buckner worked for?

Jared Buckner has worked for Nvidia, Ampere, Qualcomm, Freescale Semiconductor, and The School Of Civil And Environmental Engineering At The Georgia Institute Of Technology (Ceeatgt).

Who are Jared Buckner's colleagues at NVIDIA?

Jared Buckner's colleagues at NVIDIA include Sreedhar Chikoti, Shounak Deshpande, Adrienne C., Ramin Mirzahosseini, Ph.D., and Sujith Solleti.

How can I contact Jared Buckner?

You can use AeroLeads to view verified contact signals for Jared Buckner at NVIDIA, including work email, phone, and LinkedIn data when available.

What schools did Jared Buckner attend?

Jared Buckner holds Bs, Electrical And Electronics Engineering from Georgia Institute Of Technology.

What skills is Jared Buckner known for?

Jared Buckner is listed with skills including Embedded Systems, Debugging, Verilog, Soc, Vlsi, Perl, Asic, and Eda.

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