Jared Lee Email & Phone Number

San Diego, California, United States

To technically support, sell, and proliferate the Cadence Semi-Conductor Software platform to our current and potential customers. This includes doing semi-conductor design, methodology development, tool evaluations, software product development, account management, and engineering management of all resources within product area across North America and regional accounts. This includes all aspects of high level synthesis, synthesis, logical equivalency, physical design, and signoff in digital design. This includes Cadence's Stratus HLS, Genus, Conformal, Modus, Innovus, Quantus, Tempus, and Voltus.

Southern California

To technically support, sell, and proliferate the Cadence Semi-Conductor Software platform to our current and potential customers. This includes doing semi-conductor design, methodology development, tool evaluations, software product development, account management, and engineering Management of all resources within product areas for North America and regional accounts. This includes all aspects of high level synthesis, synthesis, logical equivalency, physical design, and signoff.

Portland, Oregon Area

Designed and developed advanced design nodes for RTL2GDS technology tool support and flows. Developed and delivered many customer training courses. Developed customer scripts and work closely with internal R&D to design and develop solutions for complex silicon designs. Expert in Digital Implementation Design, Sales, and Support. This includes synthesis, formal verification, physical design, and signoff.

Portland, Oregon Area

Over 30+ Tapeouts in silicon design with Intel corporation. Designed and developed, GPU's, Chipsets, ASIC's, Flash, and CPU's. Developed RTL for Chipsets. Implemented designs in Synthesis, Floor-planning, Place and Route, Clock Tree Synthesis. Analyzed designs for Design Constraint Validation, Static Timing Analysis, Power Analysis, LVS, DRC, LEC. Highly sought after RTL2GDS designer.