Jay Baker Email & Phone Number

Cambridge, England, United Kingdom

Working in the GPU Group on physical implementations for RTL proving and qualification.My role includes leading a highly skilled and experienced team of Implementation Engineers for leading edge GPU IP. It also involves speaking to partners and other teams with in Arm to help address any questions they may have around implementation.I also work closely with EDA vendors to ensure we are not only using the latest tools available but utilising them effectively to deliver high quality, robust IP.

Cambridgeshire, England, United Kingdom

Working in the GPU Group on physical implementations for RTL proving and qualification.My role includes leading a highly skilled and experienced team of Implementation Engineers for leading edge GPU IP. It also involves speaking to partners to help address any questions they may have around implementation.I also work closely with EDA vendors to ensure we are not only using the latest tools available but utilising them effectively to deliver high quality, robust IP.

Cambridge, United Kingdom

Working in the GPU Group on physical implementations for RTL proving and qualification.My role includes leading a highly skilled and experienced team of Implementation Engineers for leading edge GPU IP. It also involves speaking to partners to help address any questions they may have around implementation. I also work closely with EDA vendors to ensure we are not only using the latest tools available but utilising them effectively to deliver high quality, robust IP.

Cambridge, United Kingdom

Working in the GPU Group on physical implementations for RTL proving.My role also includes leading a highly skilled and experienced team of Implementation Engineers for leading edge GPU IP.

Cambridge, United Kingdom

Media Processing GroupResponsibilities include leading a sub-team for Display and Imaging activities, IP implementation and flow proving.

Kings Langley

Layout of SoC designs, top-level & block level including P&R, CTS, STA & Physical verification.

Layout of SoC designs, top-level & block-level including P&R, CTS, STA & Physical verification.

Layout of SoC designs, top-level & block-level including P&R, CTS, STA & Physical verification.

Test chip designs top-levels and block-level including P&R, CTS & Physical verification

PCB Layout of Digital and Analog designs for PC Graphics, Audio and Home entertainment systems. Also Mechanical assembly drawings.

PCB layout engineer for Digital, Analog & RF designs, including mechanical drawings and maintenance of the components database.