• Analyzed multiple HDD and SSD DDR2/3/4, NAND Flash and SAS interfaces using HSPICE, Sentinel-SSO, and ADS• Created verification tool to quickly check cross talk and propagation delay and produce a LaTeX based analysis report in wide-band and s-parameter based package models• Analyzed PCB and package power integrity using SIwave, HSPICE, and Sentinel-SSO• Developed timing budget for NAND flash SoC interface• Worked with SoC and package design to optimize wirebond and flipchip… Show more • Analyzed multiple HDD and SSD DDR2/3/4, NAND Flash and SAS interfaces using HSPICE, Sentinel-SSO, and ADS• Created verification tool to quickly check cross talk and propagation delay and produce a LaTeX based analysis report in wide-band and s-parameter based package models• Analyzed PCB and package power integrity using SIwave, HSPICE, and Sentinel-SSO• Developed timing budget for NAND flash SoC interface• Worked with SoC and package design to optimize wirebond and flipchip BGA, DRQFN, and QFP packages for signal and power integrity• Designed and developed automated process to perform Peak Distortion Analysis to quickly evaluate and optimize wide range of system configurations first in MATLAB and then translated into Perl• Performed what-if signal integrity analysis for NAND flash system design and reported results with recommended next steps and possible mitigation to internal and external design teams• Developed flexible analysis and post-processing engine utilizing HSPICE and GNUplot to analyze SerDes package designs (SATA, SAS, PCIe, Read Channel, USB) to replace slow and costly ADS framework• Analyzed PCB and package EMI with SIwave• Extended internal JEDEC/ONFI/Toggle compliance tool to output statistical reports on simulations to allow deeper view of trends and outliers in simulated systems• Aided group members triage HSPICE and high-priority SI issues• Analyzed low-cost HDD SoC DDR2/3 interface• Presented SI analysis results to internal design team and external customer• Updated PCB layout guide for HDD SoC DDR• Investigated package/die resonance impact on timing• Correlated SIwave PCB model with TDR measurements Show less

• Guided students to understand key concepts and gain design skills in ECEN5613 Embedded System Design• Evaluated student lab assignments

• Prepared monthly and year-end reports for New Business Margin and existing for fixed annuities with over $1Bn in value using extensive Excel skills• Maintained C++ fixed annuity model

• Designed and implemented MATLAB tool for analyzing and checking compliance of DDR and DDR2 data and address timing and voltage from oscilloscope measurements• Developed validation and test plans for DDR, DDR2, PCIE, SATA interfaces• Simulated DDR and DDR2 and developed and presented routing guidelines for internal and customer use, based upon simulation and system validation• Evaluated hardware needs to measure and evaluate PCIE Gen 1, SATA Gen 1 and memory interfaces on new… Show more • Designed and implemented MATLAB tool for analyzing and checking compliance of DDR and DDR2 data and address timing and voltage from oscilloscope measurements• Developed validation and test plans for DDR, DDR2, PCIE, SATA interfaces• Simulated DDR and DDR2 and developed and presented routing guidelines for internal and customer use, based upon simulation and system validation• Evaluated hardware needs to measure and evaluate PCIE Gen 1, SATA Gen 1 and memory interfaces on new control processor• Advised technical marketing and customers on layout of development and DDR implementations• Coordinated freeze of processor pad ring, package routing and ball placement for control processors and companion chips and was responsible for designating their pin-out• Led effort to ensure reliable manufacturability of PCB with 0.5mm BGA• Defined requirements for I/O in silicon for DDR/DDR2 and PCI• Debugged DDR signal and logic errors with oscilloscope and logic analyzer• Developed MATLAB scripts to automate correlation of SPICE I/O models to silicon measurements taken in lab• Created infrastructure to generate IBIS models from SPICE, correlate IBIS model to SPICE and generate correlation reports of IBIS models Show less