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Jay Jadav Email & Phone Number

Senior Logic Design Engineer at Microsoft |Ex SoC Design Intern at Intel |MS in Computer Engineering USC'19 at Microsoft
Location: Sunnyvale, California, United States 8 work roles 4 schools
1 work email found @microsoft.com LinkedIn matched
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Current company
Microsoft
Role
Senior Logic Design Engineer at Microsoft |Ex SoC Design Intern at Intel |MS in Computer Engineering USC'19
Location
Sunnyvale, California, United States
Company size
231118 employees

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Jay Jadav is listed as Senior Logic Design Engineer at Microsoft |Ex SoC Design Intern at Intel |MS in Computer Engineering USC'19 at Microsoft, a company with 231118 employees, based in Sunnyvale, California, United States. AeroLeads shows a work email signal at microsoft.com and a matched LinkedIn profile for Jay Jadav.

Jay Jadav previously worked as Senior Logic Design Engineer at Microsoft and SoC Design Engineering Intern at Intel Corporation. Jay Jadav holds Master Of Science, Computer Engineering from University Of Southern California.

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{first}.{last}@microsoft.com
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About Jay Jadav

Current Microsoft - Logic Design Engineer at Microsoft.• Patent filed with US Patent office as co-inventor with 2 team members for "FLEXIBLE SRAM PRE-CHARGE SYSTEMS AND METHODS" with filing number - (MS# 412567-US-NP) on 1/13/2023.• Front-end RTL Design Lead/Owner for Cluster SRAM design for next Gen AI chips and wrote microarchitecture specification involving features, performance, area, power savings efforts for design & implemented uArch Logic design for the same, along with constant collab with Arch, DV, PD, CKT, DFT and power team.• Part of Microsoft's first in house AI accelerator Maia 100 chip's Silicon Validation team for HBM (High Bandwidth Memory) block Validation and did characterization testing for the HBM block and I am glad to be part of first in-house AI chip development for Microsoft.• Involved in front end RTL design of L2 cache and bus interfaces with clock crossings based on architecture specs.• Design, simulate, synthesize design for timing, debugging/fixing bugs, making improvement in design for timing, performance and power, writing assertions and coverage for the IP’s and developing python scripts to automate file generation. Collaborate with various teams for design challenges, changes and suggesting improvements in design implementation.Past experienceIntel - SoC Design Intern in the Programmable Solutions Group (PSG).Part of front end RTL Design team, contributing to RTL level implementation of micro architecture specs using verilog of peripheral IP's such as timers, IO's, memories, debug controller, etc.Performing IP simulation and verification using Synopsys Verdi, Design Compiler, Spyglass Lint, checking for timing checks such as clock domain crossing of the synthesized blocks.Integration of local IP's to the top level of the chip. University and CourseworkI did my Masters in Computer Engineering specializing in Computer Architecture and VLSI Systems from University of Southern California with GPA of 3.6/4In my Master's curriculum, I have taken courses which make me proficient in the areas of Computer Architecture, Physical Design, Logic Design, RTL Design, VLSI design and Digital Systems Design.Coursework:EE457 - Computer Systems OrganisationEE560L - Digital System DesignEE477L - MOS VLSI Circuit DesignEE577A and EE577B - VLSI System design CSCI 570 - Analysis of AlgorithmsEE542 - Internet and Cloud Computing Hard working, Reliable, Good Team player and Fast Learner.

Listed skills include Verilog, Computer Architecture, Pcb Design, Embedded Systems, and 38 others.

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Microsoft
Microsoft
Senior Logic Design Engineer at Microsoft |Ex SoC Design Intern at Intel |MS in Computer Engineering USC'19
Sunnyvale, CA, US
Website
microsoft.com
Employees
231118
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8 roles

Jay Jadav work experience

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Senior Logic Design Engineer

Current
Microsoft

Redmond, Washington, US

  • Front-end RTL Design Lead/Owner for Cluster SRAM design for next Gen AI chips and wrote microarchitecture specification involving features, performance, area, power savings efforts for design & implemented uArch Logic.
  • Part of Microsoft's first in house AI accelerator Maia 100 chip's Silicon Validation team for HBM (High Bandwidth Memory) block Validation and did characterization testing for the HBM block and I am glad to be part of.
  • Patent filed with US Patent office as co-inventor with 2 team members for "FLEXIBLE SRAM PRE-CHARGE SYSTEMS AND METHODS" with filing number - (MS# 412567-US-NP) on 1/13/2023.
  • Involved in front end RTL design of L2 cache and bus interfaces with clock crossings based on architecture specs.
  • Design, simulate, synthesize design for timing, debugging/fixing bugs, making improvement in design for timing, performance and power, writing assertions and coverage for the IP’s and developing python scripts to.
Feb 2020 - Present

Soc Design Engineering Intern

Intel Corporation

Santa Clara, California, US

Supporting technical leadership in the overall definition, design, implementation, verification, and documentation for SoC sub-system development.Logic design of large sub-systems consisting of high performance, low power multi-core CPUs, NOC/Fabric, high speed I/Os, and peripherals including integration of several Intel internal and external IPs. Support.

May 2019 - Dec 2019

Mixil Research Assistant (Pcb Design & Instrumentation)

University Of Southern California

Los Angeles, CA, US

Worked at the MiXIL (Microwave systems, Sensors and imaging lab) as a research assistant in the SoilSCAPE (Soil Moisture Sensing Controller And oPtimal Estimator) project with Prof. Mahta Moghaddam and various Phd students.Designed PCB boards, interfaced sensors(TEROS 12, TEROS 21, ATMOS 41) with the main end node devices for the soil moisture.

Jun 2018 - May 2019

Pcb Design Intern

Systems Creator - India

IN

Improvised working of LED driver buck - boost circuits, PCB layout routing using Eagle and assembling of floor led’s.Increased Reliability and efficiency of drivers by modifying design with team and upgraded stability in system.

Jun 2017 - Dec 2017

Embedded System Design Intern

Advanced Control Data Machines

Devised Circuits and PCB’s for 8051 based AT89c51 microcontroller board, programming and interfacing to sensors,and coded Visual basic functions for Microsoft applications such as Excel and Outlook for colleagues in office.

Dec 2013 - May 2014

Hardware Test Engineer Intern

Smartlink Network Systems Limited

Enhanced skills of utilising software for flashing firmware on IC chips of PC, Laptop motherboards and networking devices such as Routers, hubs, switches as well as detected and solved hardware problems.

Oct 2012 - Dec 2012

Research And Development Engineer Intern

Technophilia

Mumbai, Maharashtra, IN

-Embedded C programming of Atmel motherboards and run-time emulation of software on hardware.Modeled circuits for Electronic sensors such as sound, ultrasonic, proximity on Atmel Atmega8L controller boards. Performed functionality test on motherboards and was involved in procurement of electronic components.

Jun 2012 - Sep 2012
Team & coworkers

Colleagues at Microsoft

Other employees you can reach at microsoft.com. View company contacts for 231118 employees →

NA Nooli Anand Nooli Anand Colleague at Microsoft Redmond, Washington, United States, United States View → NG Nicu Gabriel Nicu Gabriel Colleague at Microsoft Altenstadt, Hesse, Germany, Germany View → SJ Simon Jun Simon Jun Colleague at Microsoft Paris, Île-de-France, France, France View → SC Sitong Che Sitong Che Colleague at Microsoft Greater Seattle Area, United States, United States View → JO Jual Obat Levitra Cialis Maxman Procomil Spray Suprema Asli Di Bekasi Cod Jual Obat Levitra Cialis Maxman Procomil Spray Suprema Asli Di Bekasi Cod Colleague at Microsoft Bekasi, West Java, Indonesia, Indonesia View → BC Bjorn Coppens Bjorn Coppens Colleague at Microsoft Velden, Bavaria, Germany, Germany View → BA Brenda Araújo Brenda Araújo Colleague at Microsoft Rio De Janeiro, Brazil, Brazil View → VB Vijaya Bhargavi Vijaya Bhargavi Colleague at Microsoft Hyderabad, Telangana, India, India View → OB Ozi Boms Ozi Boms Colleague at Microsoft Durham, North Carolina, United States, United States View → MR Mckenna Robinson Mckenna Robinson Colleague at Microsoft Denver, Colorado, United States, United States View →
4 education records

Jay Jadav education

Master Of Science, Computer Engineering

University Of Southern California

Bachelor Of Engineering, Electronics Engineering

Dwarkadas J. Sanghvi College Of Engineering

Diploma, Digital Electronics

Shri Bhagubhai Mafatlal Polytechnic

Ssc

Smt. J.B.Khot High School No. 2
FAQ

Frequently asked questions about Jay Jadav

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What company does Jay Jadav work for?

Jay Jadav works for Microsoft.

What is Jay Jadav's role at Microsoft?

Jay Jadav is listed as Senior Logic Design Engineer at Microsoft |Ex SoC Design Intern at Intel |MS in Computer Engineering USC'19 at Microsoft.

What is Jay Jadav's email address?

AeroLeads has found 1 work email signal at @microsoft.com for Jay Jadav at Microsoft.

Where is Jay Jadav based?

Jay Jadav is based in Sunnyvale, California, United States while working with Microsoft.

What companies has Jay Jadav worked for?

Jay Jadav has worked for Microsoft, Intel Corporation, University Of Southern California, Systems Creator - India, and Advanced Control Data Machines.

Who are Jay Jadav's colleagues at Microsoft?

Jay Jadav's colleagues at Microsoft include Nooli Anand, Nicu Gabriel, Simon Jun, Sitong Che, and Jual Obat Levitra Cialis Maxman Procomil Spray Suprema Asli Di Bekasi Cod.

How can I contact Jay Jadav?

You can use AeroLeads to view verified contact signals for Jay Jadav at Microsoft, including work email, phone, and LinkedIn data when available.

What schools did Jay Jadav attend?

Jay Jadav holds Master Of Science, Computer Engineering from University Of Southern California.

What skills is Jay Jadav known for?

Jay Jadav is listed with skills including Verilog, Computer Architecture, Pcb Design, Embedded Systems, Microcontrollers, C, Cadence Virtuoso, and Asic.

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