This is the same role/position when working for the company Micron. Texas Instruments bought the Lehi, Utah location from Micron.

As the Senior Manager, I was responsible for creating and executing the strategic direction for my organization to manufacture our Photolithography processes to enable maximum product yield capability on 1st and 2nd generation 3DXpoint technologies. I managed an organization of ~15 team members and 2 managers in improvement of key Process Engineering performance indicators (KPIs) around cost, output, quality and yield related to ASML Scanners and TEL Tracks.Notable Achievements Include:● Reorganized the team to support distribution of step level ownership, system champions and balance the Manager to team member ratio which enabled better engagement in Fab critical needs.● Created an environment of motivation to foster team members engagement to the fullest of their potential.● Prioritized the execution of process release on FOAK and SOAK tool qualifications for 3DXpoint technology 1st and 2nd generation needs for output. ● Initiated contingency planning for 193i down tool events on critical stacked overlay 3Dxpoint patterning levels which successfully enabled hitting Fab output commitments during unexpected tool long term downs.● Transitioned the team from reactively to proactively looking for and implementing detection improvement opportunities to minimize quantity of product at risk for deviation events.● Supported another Fab in the Micron network with resources from my team to complete setup work to enable redundant tool releases for a planned factory ramp.● Lead the 'Earthquake Preparedness' project as part of the Business Continuity program specifically for AMHS, Diffusion and Photo.● Guided and directed the entire Process Engineering organization through the 'Systems Transition' logistics as part of the site sale to Texas Instruments.

This is the same role/position when working for the company IM Flash Technologies. IM Flash Technologies was a joint venture between Intel and Micron. Micron bought out the joint venture - so the name on the building changed to Micron.

As the Section Manager, I was responsible for creating and executing the strategic direction for my organization to manufacture our Diffusion processes as fast and cheap as possible – ensuring that our product is of high yield and quality, on a technology that no one else in the world developed or manufactured – 3DXpoint. I managed an organization of ~25 team members and 3 managers to drive the process optimization and tactical needs for AMAT, Kokusai, TEL, LAM and ASM workstations.Notable Achievements Include:● Successful in partnering the Manufacturing and Process Engineering Diffusion teams to help drive a Quality culture which has resulted in furnace batch scrap reduction of 90%, which was a record low for the Fab. This low scrap performance was maintained under my leadership.● Drove the team to revise our 3DxP Technology FMEAs which resulted in proactive projects for Occurrence/Detection improvements.● Sponsored a Fab cross functional team in driving 3DxP CMOS defect reductions to a baseline low and best in network for any Micron Fab. ● Sponsored a supplier head-to-head tool evaluation that led to a $20,000,000 in cost savings for the Fab.● Led a strategic project to define and implement a 'Workstation Health' dashboard for all Fab areas. With this project I also influenced the partnership and collaboration between Manufacturing and Process Engineering departments to drive improvements to the dashboard metrics.Consistent feedback in my performance annual reviews call out great strengths with my negotiation and influencing skills not only within my direct team, but also between organizations. I repeatedly demonstrate the ability to identify gaps and drive closure regardless of my area of responsibility or expertise.

Managed a team of seven brilliant Engineers in the creation, implementation and continuous improvements of automated process control systems (run to run) for NAND Flash technology in high volume semiconductor manufacturing. My team regularly used EWMA & State Space for MIMO and SISO applications. We also developed solutions for use at our site in non-threaded control and virtual metrology.Over a three year period I led the team out of 'firefighting' mode to being strategic in understanding and driving improvements in the health of our deployed control systems. This resulted in our site being the benchmark in the Micron network for R2R health metrics. I developed and promoted two team members to ‘Senior Engineer’, reduced the overall time for new hires to assume area ownership R2R responsibilities, and invigorated the positive morale of the entire team.Beyond the technical aspect, I consider myself a strong 'people' manager. I am dedicated to seeing my team members succeed, reach new potentials and be recognized for the work they do. I have also been involved in guiding, mentoring and developing others outside my direct organization by being a summer internship program assistant in 2012, 2013, 2014 and an Emerging Leader coach for program years 2014 and 2015.

· Daily interaction with PE, PI, YE, PYA, QA and process engineering groups to ensure questions and concerns are addressed and low yield issues are eliminated to the best of our ability. I work with the appropriate parties to give lower volume products the attention they need given the situation. This has resulted in leading several cross area engineering focus teams to indentify root cause and fix for probe yield issues.· On a weekly basis I update probe yield prediction forecasts for five different parts. These forecasts have to account for known yield downsides still in the fab, potential downsides in yields seen from probe test limit changes and potential yield upsides from conversions being run. Every week the probe yield performance delta to our original business plan has to be understood and a plan laid out on what steps are in place and how long it will take to drive to business plan yields to ensure we have enough die out of the fab for our Intel/Micron parents.· Investigate single lot and/or integration weakness yield fallout material to ensure we understand root cause and have an implemented fix. Many of these investigations have involved technical paper research and experimentation on topo/production material to prove out theories and fail models. My work has personally helped strengthen the integration margin for the BEOL flow on NAND technologies.· I initiated and lead a mentoring program between Fab2 Process Integration Engineers and Technicians. The goal of the program is to provide our current PI Technicians with the training need to develop the knowledge and skills to become future Engineers and be more confident with the decision making involved in their current daily duties. After only four months of this program the quality and quantity of reports being written by our PI Technicians has dramatically improved, and they are getting involved in more engineering level projects.

· Daily monitoring of inline CD’s, defectivity, param, probe and ESDA trends to ensure maximum end of line yield can be achieved on NAND 60/70 series.· Identified a key weakness in the 55DRY (193nm) lithography process conversion of mask height loss for NAND 70 series which was resulting in broken bit lines. I personally worked with Fab2 dry etch to develop a pitch doubled spacer etch process similar to what we developed for NAND 60 series word line. The new etch process was the final integration pieces needed to continuously match process yields between 55WET(193i) and 55DRY (193nm) lithography process bundles.· Trained IMFS PI engineers on site in Lehi on the 70 series bit line module to ensure a successful start up in Fab10. I helped solve line down integration issues as needed for Fab10.

Daily monitoring of inline CD’s, defectivity, param, probe and ESDA trends to ensure maximum end of line yield can be achieved on NAND 60 series.Close relationship with Micron worldwide process integration engineers and R&D process engineers for cross fab learning, fab matching and continuous process enhancement opportunities.Support Product Eng to understand back end failures, help correlate to a fab process & provide a fix. Supported numerous fab process changes for cost savings and capacity needs - many changes did require flow re-integration.Work closely with photolithography engineers in Fab2 / Fab4 (R&D) to re-develop 51L reticles (pitch doubled word line space formation). Multiple lithography reticle designs for the array & shark jaw layout were tested & optimized across 33WL, 34WL, & 66WL part types for NAND 60 series high volume Mfg. This effort created a yielding process window for space imbalance. This improvement was implemented in all IMFT/Micron run fabs using NAND 60 series technology.Re-developed the word line etch module with Fab2/Fab4 (R&D) etch engineering for NAND 60 series technology at 34nm. Etch re-engineering resulted in high volume yields achieving >85%. Implemented in all IMFT/Micron run fabs using NAND 60 series technologies.Re-developed pitch doubled spacer etch process with Fab2 etch engineering for word line module to provide a more uniform spacer height across wafer resulting in increased mask height margin at the wafer edge where broken word line yield fallout occurred first. This process change also reduced line imbalance which increased the size of smaller word lines and reduced slow to program failures. Lead a team of integration and process engineers to reduce 43-53 TiSi defects seen on 60 series. 43L photo and etch improvements for contact size reductions and 43/53/51/45 level photolithography overlay improvements completely eliminated this fallout on the 60 series yield pareto in Fab2.

· Successfully transferred the word line module of L52A from Fab4 to Fab2. Ensured all processes were transferred and set up to match Fab4 processing. Continual efforts to remain aligned with Fab6 processing where applicable.· Constant interaction with Fab2 and Fab4 photo team to make Immersion Lithography manufacturing friendly. Identified Fab2 Immersion toppling pattern issue as a delay time before photo processing – immediate containment solved a top fab yield loss issue.· Responsible for running SWAP lots between Fab2 & Fab6 to compare the pitch doubled process to Immersion Lithography for yield learning purposes. Initial SWAP lots helped Fab2 troubleshoot overlay issues seen from a companywide process change that didn’t affect Fab6. Root cause identified as nitride remaining on backside of wafers from not running pitch doubled process in Fab2.· Daily monitoring of inline CD’s, defectivity, param, probe and ESDA trends to ensure maximum end of line yield can be achieved from the MOL1 module on L52A.· Support Process Engineering with SWR evaluations, process improvement & cost reduction projects.

Responsible for fabrication of structure/topo material in Fab6 and delivery for use in start up of Fab2 in Lehi. Continuous interaction with Fab2 process engineering groups to communicate lot processing progress and prepare for lot use in tool/module qualifications for start up. Interaction with manufacturing for cycle time improvement and hold lot dispositions.

Co-teach a freshman seminar class that is an overview for the Electrical and Computer Engineering major at Brigham Young University. The goal of the class is to ensure college students understand all the different fields and careers they can have with an Electrical and Computer Engineering Degree. As a working professional engineer I give students a perspective of what they can do in the "real world". I consider this my 'ultimate' mentoring opportunity for aspiring Engineers.

Responsible for fabrication of high performance PowerPC Microprocessors on 0.15, 0.13 and 0.09 micron technologies. This included verification of inline electrical parametrics to ensure parts meet customer specifications and to maximize company revenue. I also monitored product end of line yield and identify rouge tools and/or processes that may be improved to maximize the number of good die per wafer.My speciality was leading a team of engineers in the transistor targeting/monitoring on 0.15, 0.13 and 0.09 micron technologies. This included monitoring inline transistor performance, and predicting final part speed and power performance to determine distributions to all microprocessor part specifications. I worked closely with product engineering and planning teams to ensure maximum speed distributions are being achieved. Investigate and improve sources of variation found in many front-end of line processes that impact across wafer transistor performance.I also participated as a device representative on fab cross functional team responsible for gate pattern uniformity improvements. The team successfully reduced etch induced variation with photo dose compensation on 0.13 and 0.09 micron technologies. This improved process robustness to account for wafer to wafer variation.

Assisted Electrical and Computer Engineering students with the design and implementation of MIPS style microprocessor. Taught weekly lectures and help sections to approximately 60 students concerning the subject material of Computer Architecture and basic Microprocessor design.

Responsible for photolithography stepper lens characterization on multiple tool sets. This data was used to mix and match scanners at different photolithography levels to reduce overall product CD and overlay variation across a wafer.