Jennifer Huckaby, Pmp Email & Phone Number

Boise, Idaho Area

• Leads a team of Program Managers within the DRAM Program Management Office organization. Responsible for achieving the targets of the programs covered by the group as captured in the project release document (schedule.
• Instructing, guiding, and supporting the team (set priorities, solve conflicts, support team with decision making and with escalations)
• Set up and track training for the team
• Drive long-term planning activities within the organization including product roadmaps that span 5+ years
• Participate in annual audits of process to ensure compliance with organizational initiatives
• Participate actively in weekly and monthly work reviews as well as program stage gates

Boise, Idaho Area

Boise, Idaho Area

• Serves as a technical interface to customers during product qualification, ramp and lifetime. Works closely with R&D, Marketing and Business Development teams to drive the implementation of new product concepts and.
• Drive the development of new products and product concepts from the initial product idea to the ramp at the customer
• Work closely with teams to identify new product concepts and ideas
• Consolidate technical product requirements across multiple customers and market segments, and align with Micron capabilities
• Responsible for Client segment roadmaps and product profolio
• Set up and direct a Product Project Team for customer specific projects

Managed $30 million 1Gb GDDR3 graphic memory product which included cost-cutting measures and additional functionality. Focus on optimizing quality, yield, and manufacturing cost to best support customer needs.Headed $20 million 512Mb GDDR3 graphic memory product to be used in the game console market as a cost-cutting, technology-shrink product from the.

Responsible for planning, organizing, and directing activities concerned with product engineering and testing related topics for GDDR3 memory device projects. Successfully lead three critical projects simultaneously with the same engineering team. Ensured that priorities were defined to successfully complete all tasks for all projects. Competent in crisis.

Responsible for circuit design and characterization of multiple memory circuit blocks and leading the design team. Managed design team during a post-Si DRAM project. Provided definition of work packages and resource allocation. Assured a proactive risk management methodology.Spent two months as design trainer for all areas of the DRAM memory chip for new.

Responsible for the physical design of memory blocks. Performed verification runs and solved errors to comply with related design rules and general quality standards at all levels from cell to top level of the chip.

M.S., Electrical Engineer

B.S., Electrical Engineer

B.S., Computer Engineer