Jesse B. Email & Phone Number

Chicago, IL, US

Chicago, Illinois, United States

• Assumed team lead for E6000 CMTS DCAM2 Arria 10 FPGA legacy design that implements coder and modulator functions for RF ports for DOCSIS downstream applications.
• Create new design architecture as needed and maintain pin out of the devices.
• Responsible for synthesis, place and route, timing closure and bit file generation for 18 FPGA variations.
• Debug issues with HW/SW integration card bringup.
• Architect register map for FPGA in SpectaReg tool as a single source for register work and code (RTL, C headers, HTML documentation).
• Regression test images in the lab before submission to loadlines.

Greater Chicago Area

Implementing a XIlinx Zynq ULTRSCAL+ FPGA for a high-speed telecommunications application. Tasks have included working with the system architects to design. We're using a workflow which includes Vivado Design Suite, Clear Case, QuestaSim. The design thus far includes the following interfaces and protocols:- Gen 4 PCIe End Point - 4 lanes- DDR4 Memory.

FPGA design and validation engineer responsible for performing the VHDL coding and simulation of the RSM Board Utility Device (RBUD2). This FPGA resides on the Router Switch Module on the ARRIS E6000 Converged Edge Router. The RBUD2 FPGA is an Altera Cyclone V device that contains a lot of general purpose registers and interfaces directly to the T2080.

Regulatory Compliance Engineer is responsible for ensuring ARRIS Cable Modem Termination System products are compliance with regulatory requirements for product safety, utility interconnection, Electromagnetic Compatibility (EMC), and hazardous substances restrictions. Working with design teams to provide guidance, evaluate designs and test for compliance..

Recruited to do hardware design for the Commercial, Government and Industrial Solutions segment ("CGISS") business unit which designs, manufactures, sells, installs and services analog and digital two-way radio, voice and data communications products and systems to a wide range of public-safety, government, utility, courier, transportation and other.

Recruited to transition a key product, the Adaptive Notch Filter (ANF), from an analog system to a digital platform. The product shift is important since the new D-ANF is projected to produce 50% of all corporate revenues by 4Q ’05

Part of a Defense Advanced Research Project team of hardware development and embedded systems development engineers perfecting the Joint Tactical Radio System (JTRS) by reducing power consumption to enable longer missions by the US Army’s field soldiers and in Airforce aerospace program.

Inherited a Packet Switching Unit FPGA design (PSU) from a retiring engineer 5-months before drop dead date with 40% of the design remaining. The goal was to design a device on the Protocol Handler of the PSU for wireless applications using a Xilinx Virtex IIe FPGA packageOn a team of 8 design engineers tasked with using IBM’s PowerPC 405 on CoreConnect.