Jesse B. Email & Phone Number

Chicago, Il, Us

Chicago, Il, Us

Chicago, Illinois, United States

Assumed team lead for E6000 CMTS DCAM2 Arria 10 FPGA legacy design that implements coder and modulator functions for RF ports for DOCSIS downstream applications.• Create new design architecture as needed and maintain pin out of the devices.• Responsible for synthesis, place and route, timing closure and bit file generation for 18 FPGA variations.• Debug issues with HW/SW integration card bringup.• Architect register map for FPGA in SpectaReg tool as a single source for register work and code (RTL, C headers, HTML documentation).• Regression test images in the lab before submission to loadlines.• Coordinated with other functional teams (Hardware, SQA, Tech Support) during the life cycle of the product and be responsible for required design modifications.• Optimized FPGA design for new feature requirements.• Work with technical support to debug customer issues.• Interface with sustaining engineers to debug factory and field issues.

Greater Chicago Area

Implementing a XIlinx Zynq ULTRSCAL+ FPGA for a high-speed telecommunications application. Tasks have included working with the system architects to design. We're using a workflow which includes Vivado Design Suite, Clear Case, QuestaSim. The design thus far includes the following interfaces and protocols:- Gen 4 PCIe End Point - 4 lanes- DDR4 Memory Controller interface- 10G XFI MAC - 3 interfaces are supported- 10G SFI Ethernet - 2 interfaces supported- Xilinx Aurora Link IP - 4 lanes- I2C Controller- Quad SPI EEPROM- GPIO - UART, Debug, LEDsTiming Analysis:- Verify that timing requirements were met for all paths in your design.- Analyze setup and hold performance for all constrained paths in the design.- Verify that operational frequencies are within component performance limits.- Analyze unconstrained paths to determine if any critical timing paths have been left unconstrained.Semifore Hardware/Software Interface Tool:- Generate standard AXI interface VHDL files for register implementation.- Generate documentation(headers, MS Docs, etc.) for software team. - Generate UVM RAL files for verification environment.- Maintain Semifore source files under document control.

FPGA design and validation engineer responsible for performing the VHDL coding and simulation of the RSM Board Utility Device (RBUD2). This FPGA resides on the Router Switch Module on the ARRIS E6000 Converged Edge Router. The RBUD2 FPGA is an Altera Cyclone V device that contains a lot of general purpose registers and interfaces directly to the T2080 processor via PCIe Gen 1. Some of the additional functions of the FPGA includes - Configure 2 Arria 10 FPGA. - Decoding serial bit streams from the EzChip Network processor to board LEDs - Provide control and status for each Upstream/Downstream client card slot - Provide reset control to Arria 10 FPGA and it's PCIe core - Provide time stamping for all client cards - MDIO interface for Network processors - Provide SFP, CFP4 control and status for PHY devices (Gear Box, Cortina) - Provide interrupts back to T2080 processor via PCIe MSI - SGMII- MDIO Interface- Creating UVM verification environment using QuestaSim UVM FrameworkThere's also a complement PBUD FPGA that resides on the rear interface card of the system. This device provides a subset of the RBUD2 functionality. The PBUD device also contains additional SPI and I2C interfaces.

Regulatory Compliance Engineer is responsible for ensuring ARRIS Cable Modem Termination System products are compliance with regulatory requirements for product safety, utility interconnection, Electromagnetic Compatibility (EMC), and hazardous substances restrictions. Working with design teams to provide guidance, evaluate designs and test for compliance. Working with regulatory agencies and their standards to define and interpret requirements and to obtain and maintain certifications.

Recruited to do hardware design for the Commercial, Government and Industrial Solutions segment ("CGISS") business unit which designs, manufactures, sells, installs and services analog and digital two-way radio, voice and data communications products and systems to a wide range of public-safety, government, utility, courier, transportation and other worldwide markets.

Recruited to transition a key product, the Adaptive Notch Filter (ANF), from an analog system to a digital platform. The product shift is important since the new D-ANF is projected to produce 50% of all corporate revenues by 4Q ’05

Part of a Defense Advanced Research Project team of hardware development and embedded systems development engineers perfecting the Joint Tactical Radio System (JTRS) by reducing power consumption to enable longer missions by the US Army’s field soldiers and in Airforce aerospace program.

Inherited a Packet Switching Unit FPGA design (PSU) from a retiring engineer 5-months before drop dead date with 40% of the design remaining. The goal was to design a device on the Protocol Handler of the PSU for wireless applications using a Xilinx Virtex IIe FPGA packageOn a team of 8 design engineers tasked with using IBM’s PowerPC 405 on CoreConnect bus architecture to shrink technology and collapse 7 FPGAs and an embedded microprocessor core onto a single device. Part of team that rolled out Lucent’s first Reuse Methodology applications. We designed a Packet Bus Multi-Access device using in-house PCI Core, Packet Bus Interface and Direct Memory Access Controller (DMAC) that was easily reusable in other designs. Authored simulation plan and compiled parts from 5 other designers before delivery to chip manufacturing.