Jody Everett Email & Phone Number

Austin, Texas Area

Austin, Texas Area

Designer working on audio Codec integrated circuits.

2004- 2009 Networking/consumer group. IC Design Engineer Level V Completed emulation of Freescale's ARM9/ARM11 based i.MX processors, using the Cadence Palladium platform. Two of the three parts are now in production.Partnered with International team to verify Boot ROM and IDE drive interface.Developed Palladium testbench and testbench peripherals.Wrote script to synthesize design and testbench into Palladium format. Developed Palladium compile and run… Show more 2004- 2009 Networking/consumer group. IC Design Engineer Level V Completed emulation of Freescale's ARM9/ARM11 based i.MX processors, using the Cadence Palladium platform. Two of the three parts are now in production.Partnered with International team to verify Boot ROM and IDE drive interface.Developed Palladium testbench and testbench peripherals.Wrote script to synthesize design and testbench into Palladium format. Developed Palladium compile and run scripts. Collaborating with Cadence application engineer, verified UART interface and USB interface using Cadence Palladium bridge boards.Solved customer issues with legacy 24-bit audio DSP processors and digital radio chips, including the DSP56362, DSP56364, DSP56366, and DSP56367.Generated production test patterns. Teamed with product engineering/test engineering teams to verify correct operation.Partnered with failure analysis, product engineering, and test engineering to resolve customer quality incidents.Coordinated with global customer's engineer to increase test coverage on digital car radio integrated circuit. Co-led effort to bring to production status Freescale's award winning FSA95601 six channel class D amplifier controller.Completed RTL design/verification, including design of special modules for analog signal control, development of tests for unexpected events such as loss of I2S signal, and providing data to analog design team.Updated C model used in verification to reflect RTL design changes.Completed FPGA implementation, including RTL development, FPGA synthesis, FPGA gate simulations, and FPGA load image generation for use on a Xilinx Virtex 4 FPGA.Completed gate level simulation, including all process cases.Generated production test patterns (functional and scan). SOC fully functional and brought to production status.FSA95601 was a winner of the EDN "Innovation of the Year" award in 2006. Show less

This position included the design, development, and production support of products design for the digitial audio market. These included class D amplifier parts and audio digital signal processor chips.

>Member of technical Staff Championed efforts to design and bring Freescale's DSP56371 and DSP56374 audio digital signal processor integrated circuits to production.Completed RTL design/verification, including design of testbench modules to verify SPI, I2C, and I2S interfaces.Interfaced with China and Australia teams to develop sub-modules and top level SOC. Coordinated with Taiwan and US suppliers to bring in necessary library parts for this design.Completed gate level… Show more >Member of technical Staff Championed efforts to design and bring Freescale's DSP56371 and DSP56374 audio digital signal processor integrated circuits to production.Completed RTL design/verification, including design of testbench modules to verify SPI, I2C, and I2S interfaces.Interfaced with China and Australia teams to develop sub-modules and top level SOC. Coordinated with Taiwan and US suppliers to bring in necessary library parts for this design.Completed gate level verification, including all process cases.Both parts met schedule and were functional on first silicon, production worthy on second silicon(metal changes only).Completed design of the scheduler block for the Freescale digital base band chip.Completed RTL design and block level verification. Collaborated with design team to incorporate scheduler block into top level SOC.Completed top level verification of the scheduler block in the SOC.Completed gate level verification of this block in the top level SOC, including all process corners.Completed preliminary gate level synthesis of the scheduler block. SOC functional on first silicon, production worthy on second silicon(metal changes only). Show less

This position included the development and productization of telecommunication and audio digital signal processor integrated circuits.

This postion incouded the development of telecommunications integrated circuits. These included devices intended for the ISDN, cellphone, and ADSL markets

This position included the development of high speed logic and telecommuications integrated circuits. These were for the general logic and ISDN markets.

Bsee, Electrical Engineering

Bachelor Of Science, Electrical Engineering