Physical Design Tcl Timing Closure Asic Static Timing Analysis Timing Processors Mixed Signal Vlsi Ic Systemverilog Logic Design Functional Verification Verilog Floorplanning Place And Route Primetime Eda Rtl Design Soc Lvs Low Power Design Drc Physical Verification Rtl Coding Vhdl Signal Integrity Logic Synthesis Cmos Integrated Circuit Design Microprocessors Cadence Virtuoso Formal Verification Hardware Architecture Application Specific Integrated Circuits System On A Chip Coaching Communication Mentoring Talent Management