John Conway Email & Phone Number

Durham, North Carolina, United States

Manassas, Virginia, United States

Manassas

Malta, Ny

• Leader of site-wide Quality, SPC/FDC, Device Performance, Yield, NPI, and Variation Improvement strategies resulting in on-time Quality ramp of 14nm products in a $15B wafer fab• Led Cross-Fab Engineering/Integration/Operations teams to define new methodologies resulting in 15% Yield improvement, including frequent executive presentations to external customers

Malta, Ny

• Led 100+ Etch managers, engineers, & technicians to meet 24x7 ownership of Safety, Quality, Output/Cycle Time, and Cost goals

Chandler, Az

 Led Litho/Etch Area Operations startup and 24x7 ramp in new R&D Pilot line responsible for developing and transferring new processes and tools.  Led Cross-Fab Yield/Quality Systems team to establish critical business processes enabling technology production readiness

Chandler, Az

 Area Engineering & Operations manager in state-of-the-art 300mm facility supporting high volume ramp of leading edge products. Led 8 managers & 150+ engineers and technicians to exceed safety, device, yield, cycle time, and cost performance goals Integrated Segment coach responsible for device targeting, yield, quality and cycle time for complex segment of 32 and 45nm process flow

Chandler Az

 Led factory OpEx Leadership team that drove 60% increase in output over 6 months thru capacity expansion, yield improvements, and tool availability gains while beating cost goals in $180M/yr factory Led team of 8 Process & Yield Engineering Groups consisting of 180+ team members to achieve Best-in-Class Yield & Output. Responsible for Litho, Etch, Thin Films, Planar, and C4 areas as well as Integration/Device and Q&R. Coordinated Multi-Factory Yield and Output improvement efforts with Product Design Divisions to resolve major product risks

Chandler, Az

 Led multinational Design/Fab/Assembly/Test /Q&R Coordination Team to deliver on-time Itanium 2 Server product launch and ramp Kicked off new x-functional team of Process Engineering, Device, and Design resulting in 50% improvement of Die Yield /Device Performance Developed systems to increase NPI load by defining improved Design for Manufacturabilty guidelines, allowing critical on-time product launches. Led 8 Layer Metal transfer team to improve Device Performance.

Chandler, Az

 Led group of 15 Litho engineers responsible for DUV steppers, Metrology, Layer Integration. Led Santa Clara Development group during 6 month assignment resulting in successful transfer to High Volume Manufacturing

Albuquerque, New Mexico Area

 Managed 8-12 engineers and technicians responsible for entire litho area including Nikon links, PI, Metrology, and DUV Cure

Manassas, Va

 Leader for x-ray lithography testing - coordinated activities between 4 IBM sites resulting in demonstration of x-ray/i-line lithography mix and match Backend Integration - Led C4 bump reliability team to resolve major customer delivery problem Lithography Engineer - Worked with other IBM sites to perform initial optimization of APEX DUV resist.