John Edson Email & Phone Number

United States

* Floorplanned and routed transmitter, receiver and DDR PHY blocks in 28nm and 12nm processes using Design Planner and ICC2. The backend flow was done using a hierarchical implementation with 3 levels of hierarchy for synthesis and place and route.* The work included developing and using flow scripts for Design Compiler for synthesis, PrimeTime for static timing analysis, Formality for formal verification, ICC2 for place and route and Redhawk for power analysis.* The work also included… Show more * Floorplanned and routed transmitter, receiver and DDR PHY blocks in 28nm and 12nm processes using Design Planner and ICC2. The backend flow was done using a hierarchical implementation with 3 levels of hierarchy for synthesis and place and route.* The work included developing and using flow scripts for Design Compiler for synthesis, PrimeTime for static timing analysis, Formality for formal verification, ICC2 for place and route and Redhawk for power analysis.* The work also included developing TCL design constraints for syntheis and P&R as well as hierarchical UPF for the power flow which included inserting power switches and connecting lower level IP blocks. Show less

Colorado Springs, Colorado

* Developed and installed scripts to perform Synthesis using Design Compiler, Static Timing Analysis using PrimeTime, Formal Analysis using Formality and Place and Route using ICC2* Floorplanned and routed transmitter, receiver and DDR PHY blocks in 28nm process using Design Planner and ICC2. The backend flow was done using a hierarchical implementation with 3 levels of hierarchy for synthesis and place and route

Colorado Springs, Colorado

* Created Modulefiles for setting up the Linux design environment used to manage the design tools and physical design kits* Created custom TCL packages used to augment the Modulefiles package* Installed and managed the design tools and physical design kits* Generated an extensive set of online documentation on how to use the Linux design environment* Developed tools for generating LEF and liberty files using the Virtuoso layout editor and SKILL including documentation*… Show more * Created Modulefiles for setting up the Linux design environment used to manage the design tools and physical design kits* Created custom TCL packages used to augment the Modulefiles package* Installed and managed the design tools and physical design kits* Generated an extensive set of online documentation on how to use the Linux design environment* Developed tools for generating LEF and liberty files using the Virtuoso layout editor and SKILL including documentation* Routed multiple design blocks (20MHz to 1.5GHz+) using TowerJazz 130nm standard cell library and the Cadence Innovus design tool Show less

Colorado Springs, Colorado

* Developed a set of TCL/Makefile packages including documentation used for synthesis, static timing analysis, formal analysis, place and route and physical verification* I used the packages to tapeout 15+ mixed signal designs using various technologies ranging from 180nm to 65nm. The designs included analog blocks, EEPROM/FLASH, RAM and ROM memories, IO's and RTL ranging from 40K gates to 250K gates with the clock rates ranging from 30Mhz to 400Mhz* Developed Synopsys Design Compiler… Show more * Developed a set of TCL/Makefile packages including documentation used for synthesis, static timing analysis, formal analysis, place and route and physical verification* I used the packages to tapeout 15+ mixed signal designs using various technologies ranging from 180nm to 65nm. The designs included analog blocks, EEPROM/FLASH, RAM and ROM memories, IO's and RTL ranging from 40K gates to 250K gates with the clock rates ranging from 30Mhz to 400Mhz* Developed Synopsys Design Compiler scripts which I used for synthesis. The scripts include DFT and UPF support* Developed Synopsys Prime Time scripts which I used for static timing analysis. The scripts were used to perform pre and post route timing analysis* Worked with the design group to generate the SDC and UPF design contraints* Developed Synopsys Formality scripts which I used for formal checking. The scripts were used to perform pre and post route analysis* Developed Cadence Encounter Digital Implementation (EDI) scripts which I used for place and route including floorplanning, placement, optimization, clock tree synthesis and routing. I used TCL to setup the EDI environment and floorplan the designs* Developed Synopsys Silicon Smart scripts which I used for block level characterization. The liberty files were used for the backend design flow* Developed Open Verification Methodology (OVM) scripts for functional verification using random vectors* Developed SKILL procedures for automating the Cadence Virtuoso design environment*Provided general CAD support including software installation and setup for the vendor tools Show less

Colorado Springs, Colorado

* Developed Cadence Diva DRC/LVS verification run sets* Developed SKILL and C programs for automating the Cadence analog and layout design environment* Generated P-Cells used to automate the layout design environment* Designed a Real Time Clock block using a set of custom gates* Setup and administered UNIX SUN systems and provided general CAD support