John Olson Email & Phone Number

Norfolk, Va, Us

Virginia, United States

Have continued to support the US Navy’s ATE systems and Test Program Sets (TPS’s). Worked on site at Lockheed Martin’s Orlando facility to resolve numerous issues with the development of the Navy’s next generation ATE system “eCASS”. Have identified and resolved numerous issues with problematic performance of eCASS instrumentation. Identified problematic behavior with Teradyne’s Digital Test Instrument (DTI), which resulted in total failure of the APG-73 Radar Receiver TPS. The problem I identified, resulted in Teradyne re-writing portions of their instrument driver for the DTI. I resolved numerous TPS issues related to migration of (now) legacy CASS TPS’s to the eCASS system. Wrote numerous updates to the CASS User’s Guide For TPS Developer’s (a.k.a T00K), related to performance of the Digital Test Unit (DTU)/Digital Test Instrument (DTI). Performed analysis of the behavior of eCASS’s Radio Frequency Signal Generators (RFSG’s), and Spectrum Analyzer System Interface (SASI), in order to identify deficiencies in their performance. Created test case programs to illustrate eCASS system problems to permit ATE system engineers to address/correct eCASS problems without the need for specific avionic and TPS hardware. Created test case programs to sweep CASS. & eCASS RFSG’s for potential “spurs” using both internal and external (via IEEE-488), Spectrum Analyzers. Reverse engineered the problematic eCASS Low Wattage Power Load (LWPL) to identify the root cause of TPS failures using the LWPL on eCASS. Am in process of assisting in an efficiency upgrade of the Universal Exciter Upgrade (UEU) TPS for Naval Surface Warfare Center (NWSC) Crane IN.

Norfolk, Virginia, United States

Assisted in the completion of the CASS TPS for the E-2C Improved IFF system. This TPS was abandoned by the contractor and has been placed under the cognizance of Fleet Support Team (FST) at Naval Station North Island CA. This task has involved an in depth reverse engineering process, as the CASS TPS was intended to replicate the functions of the legacy Grumman CAT-IIID TPS, but using Field Programmable Gate Arrays (FPGA's). I identified and corrected numerous errors in the FPGA programming. I redesigned portions of, and reloaded, the FPGA's using Altera’s Quartus II software package. I also reallocated test assets in order to mitigate conflicting use of CASS instruments which violated the ATE design specification.I participated in migration testing of numerous CASS test programs being re-hosted on the new US Marine Corps RTCASS test system. Identified problematic areas in the conversion process and submitted System Problem Reports (SPR). I also identified a multitude of issues with individual test programs and made recommendations for corrections of these programs via Problem Investigation Requests (PIR's).Completed the Reliability Improvement Program (RIP) for the F-18 APG-65 RADAR Test Program Sets. This involved the redesign of two CASS Interface Devices (ID's), an RF Test Fixture (RFTF), and several cables. I eliminated unused test points that had created destructive interference which had been causing false failures in avionics testing. I replaced low quality RF relays with higher reliability components. I updated the TPS Self Test program for both TPS ID's and the RFTF.

I performed migration testing of CASS TPS's, being translated from the original CASS systems, to newer RTCASS ATE. I identified the root cause of test failures and corrected TPMl and C test software to resolve testing transportability issues.Analyzed hardware for the TPS's supporting APG-65 radar equipment to improve reliability. I diagnosed newly re-manufactured TPS hardware and corrected numerous errors in the level-3 data package, which had delayed the delivery of much needed TPS hardware to fleet activities.I was instrumental in the completion of the APG-65 Radar Target Display Processor (RTDP) test program on CASS. Due to the lack of required testing data, I acquired RTDP assembly language data, using a logic analyzer from the legacy ATE. I then used this acquired data to develop the successful CASS TPS.Additionally, I was tasked with assisting numerous TPS developers, both contractor and government, in the resolution of ATE TPS digital and analog issues. This assistance revived many stalled TPS development projects. I implemented various avionic communications protocol emulations, and data acquisition/test algorithms, using the CASS test system's embedded Teradyne Digital Test Unit (DTU).I participated in the regression testing and correction/re-integration of more than one hundred CASS TPS's for VECP (M-900) DTU compatibility. This development, integration, and reintegration, included avionics from F-18, F-14, AV-8, S-3A, E-2C, SH-60, and EA-6B aircraft systems, such as APG-65 Radar Target Display Processor, Receiver Exciter, APG-73 Radar Receiver, JTIDS TACAN R/T, Head Up Display (HUD), Electro-Optic avionics, weapon control processors, data storage units, and flight control computers.My DTU application notes were used for presentations at the Teradyne User's Group conferences and were subsequently published in the CASS TPS Programmer's Guide (TOOK). I was responsible for submitting, investigating and resolving CASS System Problem Reports (SPR's).

Norfolk, Virginia, United States

In support of the Naval Aviation Depot in Norfolk Virginia, I developed the software/hardware interface to test F-14A VDIIHUD display processor using CASS. This included development in Teradyne VX2, ATLAS and DCL languages. Created routines to simulate aircraft telemetry and perform digital data acquisition to evaluate the unit's data processing and video symbol generation circuitry. Programmed test instruments including, but not limited to, waveform synthesizers, pulse generators, AC & DC power supplies, waveform digitizers, frequency/timer counters and multi-meters. Coordinated design and integration of a TPS for F-14A weapons control system using the Navy's HTS test system. Developed IEEE-488 program code to implement three instrument capabilities not integrated into the ATLAS environment.Developed software/hardware to test ASIC VLSI data de-compaction proto-type IC using GAl's MATE-390 system. Additional experience includes investigation of VAST and CAT-IIID software & hardware deficiencies. Developed software updates in VITAL, ATLAS, and RTE-IVE BASIC languages.

Virginia, United States

Quality Assurance Representative at U.S. Navy avionics intermediate maintenance repair facility. Responsible for ensuring the quality of avionic units tested, repaired and returned to service by the facility. Investigated ATE software/hardware discrepancies, providing recommendations to the engineering support office. Prior assignments included shift supervisor of an ATE work center, ATE bench technician and aircraft flight deck avionics trouble-shooter for F-4J aircraft during overseas deployment.