John Das Email & Phone Number

Fremont, Ca, Us

United States

Teaching science classes to middle school and high school students

San Francisco Bay Area

My appreciations for the need to establish MEMS industry standards developed during my work at NIST in 1995. I took the opportunity to reconnect with my NIST team members by joining SEMI Standard committee and to help drive and establish MEMS related standards while I was working at SVTC with a $5M budget to establish their 8 inch MEMS foundry. SEMI Standards provides me opportunities for participation and interaction with MEMS experts, establish and maintain technical proficiency, exposure to manufacturers of devices and equipment, and the development of standard test methods, guides, and specifications.

Milpitas, Ca

Managing Global Customer accounts for Developing, Prototyping, and Transferring accounts to high volume production facilities: My Accounts: Sierra Wireless, SONY, WHOOP, and RF Digital.

Livermore,Ca

R&D and Engineering Project Lead: Developed two Plasma tools for Gentle clean and Resit Strip that are on road map for market introduction.- A 13.56 MHz Gentle Plasma cleaning tool suitable for Semiconductor front end compatible plasma strip and clean and also for Wire Bond Surface Preparation and Gentle Cleaning Applications.- A 3 KW remote plasma down stream Photo Resist Strip tool. Plasma processes are suitable for Semiconductor front end compatible plasma strip and clean and descum applications. This tool is also re configurable for silicon, dielectric and metal thin film etch applications. Process Development and Demonstrations: Processes including Plasma etch, clean and surface treatment and modifications; Resist Strip and Descum: Vacuum curing and treatment of polymer films and various Thin metal film anneal for customer applications in Semiconductor, Packaging, MEMS and Wafer level packaging (WLP) for Semiconductor, Medical, Bio-medical and Hybrid packaging industries.

Demonstrated various etch processes such as, VNAND, STI, Spacer, Gate-poly, Iso-poly etch processes to our customers including Samsung and Hynix. Assisting with new generation etch tool development project with process characterization and endurance tests.

Developed MEMS based novel processes for fabricating up to 20um tall AFM probes with near vertical profiles. Developed several thick resist lithography over deep KOH etched topography and KOH etch processes for fabricating the probes. Provided manufacturing support of the various high precision silicon, nitride and metal coated AFM probes.

Developed a custom coater and developer track with AIO International for processing MEMS based custom 10 mm thick wafers. Sustained 43 um and 24 um thick BPR 100 resist processes for manufacturing various micro machined and electroplated Cu, NiCo, and Pd thick films for fabricating precision mechanical parts for medical applications and Probe tips for high density probe cards applications for key customers like Micro-probe, KI, Intel, Sam sung.

San Francisco Bay Area

Providing full complements of MEMS and Nano technology based Process and Product development consultations and foundry services from design to prototyping for small start-ups to large technology firms, particularly working in Nanotechnology, Biotechnology and Micro Mechanical Systems.

San Francisco Bay Area

Supervised two MEMS wafer foundries (Formally Cypress and SEMATECH). Supervised the $5M CapEx purchase and installation of SUSS Microtec manufactured Coater Tracks, Contact Aligner, Manual and Automated Substrate Bonders. Reviewed process capabilities of the two foundries and coordinated the as needed tool and process gap fill activities. Reviewed customer MEMS products and developed process plan and process flow for fabricating them at the SVTC foundries. Provided MEMS process solutions for Intel(NanoChip), IDT, Sun Microsystems, National Semiconductor, Fairchild Imaging, Sandisk, Aviza, Qspeed, Lumera, Nanosys and Knowles Acoustics.

San Francisco Bay Area

PRODUCT ENGINEER: Supervised the production of two key automotive pressure sensors, provided customer support and production process control, Tracked yield trends and updated PFMEA of the two pressure sensor products.DRIE ENGINEER AND SENIOR PROCESS ENGINEER: Managed a 6 inch 200 i-speeder DRIE tool for the production of automotive pressure sensors. Developed several deep Si and through wafer etch processes for the sensor diaphragm release, blood pressure sensors, Transmission fluid Pressure sensors, Accelerometers and microphones.FOUNDRY SUPERVISOR for Lilliputian Systems: Manged three operators and provided onsite production supervision for three years

San Francisco Bay Area

SENIOR PROCESS ENGINEER: Developed and integrated all fabrication processes for the MEMS based Nectar™ Mobile Power System cell phone charger at the Stanford Nano Fabrication (SNF) facilities and LLNL laboratories. Managed all aspects of process development and prototype production activity at Silicon Micro Structures, a 6 inch MEMS foundry. GRAND FATHER EMPLOYEE: Started working with the two Lilliputian's founders, Samuel Schaevitz and Aleks Franz with only one $250K initial SBIR grant, working out of Sam’s apartment office. Since then the company has raised over $150M in venture capital investments over the years. I was with the company till it moved to Boston, MA where the parts are being fabricated through Intel 8" wafer foundry and marketed through Brookstone stores in shopping centers and Airports.

San Francisco Bay Area

Developed various 3D Optical MEMS device fabrication processes at the Stanford Nano Fabrication (SNF) facilities as the only process engineer.Introduced six different Optical Attenuator (VOA) and Dynamic Gain Equalizer (DGE) products to market.

San Francisco Bay Area

PROCESS APPLICATIONS ENGINEER: Provided Rapid thermal Processes (RTP) installation and process support to major Semiconductor manufacturers in the mid west region. Provided process support for the development of the HEATpulse 8800 RTP Beta tools installed at SEMATECH and at Sandia National Laboratories.SENIOR PROCESS ENGINEER: Assisted in the development of the STEAMpulse RTP tools for the added O2 rich and H2 rich wet RTP process capability using Pyrogenic and Catalytic converted steam generators. Developed and demonstrated various patented wet steam and dry Rapid Thermal Processes (RTP) for major semiconductor manufactures.

Joined the NIST & University of Maryland's MEMS team and worked on developing high G accelerometers and Dynamic Scene Simulators using PolySi thermal pixel arrays. Developed multiple die attach/Butting technique for increasing the display pixel array by attaching four smaller chips. Developed XeF2 etched pixel release processes and high G accelerometers packaging process using flexible polymer substrates. Work supported by the U.S. Navy.

Developed several processes related to Si micro-machining and the development of silicon field emission cathodes. Fabricated single cathode and addressable array cathodes on silicon substrates as well as suspended movable micro-mechanical structures and suspended micro-heaters with integrate feedback resistors to further enhance cathode performance

Taught "Signals and Systems" to a junior class of 42 students (8/90 - 12/90)Taught "Instrumentation" to a senior class of 23 students (8/87 - 12/87)

Research Associate Professor, Advanced Technology (Ee)

Research Topic: Interface studies of metal films on dielectric insulators. Work supported by IBM. Dissersation research conducted.

Doctor Of Philosophy - Phd, Advanced Technology

Bsc, Applied Physics And Electronics

Activities and Societies: Graduated with the highest Honor ( First Class First position)

Msee, Electrical And Electronics Engineering