I am an experienced professional in verification flows and environments, specializing in achieving efficient and safe verification closure. I bring a wealth of expertise in UVM, constrained random coverage-driven testing, and RTL development using both VHDL and SystemVerilog.I excel in leadership, project management, and cross-department communication. My skills also include FPGA backend work and tooling expertise for RTL simulators and compile flows. I thrive in high-paced work environments and am known for my positive, dedicated, responsible, and inventive approach, which is reflected in my strong work ethics.