Jonathan Avey Email & Phone Number

Greater Vancouver Metropolitan Area

I/O Hub Architect.

Burnaby, British Columbia, Canada

- Subsystem and Subsystem lead on multiple projects.

120G OTN Processor - Developed architecture for Multiplexing and De-Multiplexing of OTN traffic (ITU-T G.709, G.798) - High-speed and multi-million gate design- Architecture features included hitless packet traffic scaling with ITU-T’s G.hao/G.7044- Completed detailed architecture and design of multi-million gate OTN traffic Multiplexor design- Completed detailed architecture and design of hardware and software for configurable switching algorithms (Matlab based)- Planned and coordinated sub-component architecture and design for reuse within multiple subsystems over multiple working sites (Burnaby, Bangalore, Montreal)- Coordinated, planned, and debugged architecture and design with Verification team- Planned and debugged with Software, Emulation, and Validation teams- Performed synthesis, static timing, ECO, and LEC

2.4GHz 802.15.4/Zigbee SOC with ARM Cortex-M3 (EM3xx)-Developed overall specification with digital and software teams. -Responsible for detailed design and implementation of the MAC, AES security, and ADC-Performed top-level verification of the 802.15.4 MAC, security (AES and associated wrapper), CPU, RAM controller, and power management features.-Completed code coverage and gate level verification.-Conducted static timing analysis of serial ports. -Developed ECO's with back-end team late in the design cycle and modified portions of design for power savings. -Utilized Matlab to build test cases for characterization of all digital features within the silicon.-Modified existing software drivers for use with Matlab and JTAG debug hardware. 2.4GHz 802.15.4/Zigbee SOC with XAP2 core (EM250 & EM260)-Generated requirements, specification, design and implementation of 802.15.4 MAC and security. MAC included back-off mechanisms, network slotting, automatic acks, address filtering, DMA interface, and network debug features.-Conducted verification of chip test modes and production of test vectors post silicon. -Collaborated with digital and software teams to determine product requirements, specification, design, implementation, and testing.2.4GHz 802.15.4 RF transceiver ASIC (EM2420)-Worked with digital and software teams to develop product specification. -Responsible for design, implementation, and testing of on chip security based around AES IP core. The implemented security wrapper functioned on a packet wide basis when transferred to RAM via serial port. -Performed top-level verification and post silicon validation testing. -Wrote and tested embedded device drivers for transceiver on Atmel ATmega128.FPGA baseband -Developed an 802.15.4 baseband from initial 802.15.4 specification. -Designed, implemented, and tested the digital baseband including correlator and clock recovery on an Actel-based ProASIC FPGA.

-Key team member in R/D project that measured channel characteristics of OFDM communication. Worked closely with project partners from product initiation to completion.-Developed test plan, took measurements of communication channels, managed data reduction, and wrote final project report. -Provided onsite customer support for integrating Intellon chip-sets into products; including support for board design, layout, and bring-up assistance. -Provided pre-sales engineering support.

Worked through ASIC back-end design flow with large chip design. Worked with Perl scripting, UNIX, front-end, and back-end ASIC design tools.

Bachelor Of Science, Computer Science

Electrical Engineering

Concurrent Electrical Engineering and Computer Science Degrees