Jonathan Ho Email & Phone Number

Markham, Ontario, Canada

Markham, Ontario, Canada

Toronto, Ontario, Canada

Markham, Ontario, Canada

•Develop and execute pre-silicon high speed I/O IP development plans from concept phase to tapeout •Manage IP design deliverables to SOC, including IP integration, verification coverage and design QoR •Identify design risks such as architecture and coverage gaps and provide mitigation plans•Act as IP focal point to SoC; triage and drive IP related issues to closure•Lead new IP design initiatives to improve IP power and area efficiency

Toronto, Canada Area

•Manage a virtual team of RTL design and FW engineers to provide high speed I/O IP design support •High speed I/O IPs include PCIe Gen4, xGMI, IOMMU and I/O root complex and SATA•Work with SOC architects to explore performance and cost trade-off on SOC architecture •Propose and drive firmware architecture changes on future SOCs •Provide technical direction on complex silicon debug and create complex production workarounds•Architected and implemented industry’s first PCIe Gen4 ESM solution

Markham, Ontario, Canada

• Manage a team of engineering leads with a mandate of leading the GPU SOC programs from design phrase to first customer ship (FCS)• Provide technical leadership on hardware, software, firmware verification planning• Focal point of program alignment and provide priorities when resource conflicts arise• Drive architectural changes to overcome design limitation to meet product requirement and schedule• Supervise the overall performance and optimization efforts to ensure product competitiveness• Create technical project budget, schedule and WBS; assess risks due to manpower and coverage shortfall, and provide mitigation recommendations to management

Toronto, Canada Area

•Lead Post-silicon bring-up and feature enablement efforts on Ryezn and EPYC CPU products•Focus on I/O, virtualization and SoC management IPs, provide technical leadership on test plan development, emulation debug, post-silicon feature enablement and validation methodology•Define I/O performance and power verification methodology, provide technical guidance on achieving key metrics•Create technical project budget, schedule and WBS; assess risks due to manpower and coverage shortfall, and provide mitigation recommendations to management

Toronto, Canada Area

•Lead IP bring-up on I/O (PCIe, HyperTransport, AXI), RAS and virtualization IP blocks•Design and execute bring-up plans to verify features at pre and post-silicon stage; debug hardware and software issues through scan dumps, bus traces, waveform and RTL debug•Act as first responder to triage general system level issues such as hangs, performance degradation, and poor power savings•Provide consultation to software and validation teams on their feature enablement plans•Coordinate with supporting diagnostics, firmware and driver teams to drive software issues to closure; develop debug scripts to speed up debug process•Track and provide status updates related to issue investigation and feature found during bring-up

Working on bringing-up and debugging ASIC IP blocks for AMD products

•Managed the SLT (System Level Test) stage for AMD's Chipsets and graphics ASICs manufacturing•Developed new SLT flow to cover new ASIC features such as USB3 and PCIe gen2•Provided optimal test strategy through tradeoff analysis between test coverage and cost; won AMD Spotlight award for GPU test cost reduction•Resolved all ASIC production issues such as yield instability and high failure rate at customers•Drove software and hardware delivery schedule from multiple teams to keep production on track

Toronto, Canada Area

•Developed hardware diagnostics for AMD’s Chipsets, Discrete Graphics and Multimedia (TV tuner) products in C and C++ •Designed Windows diagnostics tools for TV Tuner and Discrete Graphics products (in MFC)•Managed diagnostics projects for ASIC bring-up, manufacturing, ODM and OEM uses; Interfaced with customers and manufacturing test houses to support their specific requirements•Debugged ASIC related hardware issues on in-house and customer board designs

Toronto, Canada Area

•Circuit and PCB design and debugging for a graphics card memory testing station•Resolved memory related board issues including video corruption and timing issues•Performance analysis on DDR1, DDR2 and GDDR3 memories for ATI latest graphics boards•Participated in resolving memory power consumption issues with laptop ODM

Toronto, Canada Area

•Implemented new debug POST code feature for ATI PC display drivers (in C) Debugged issues with display drivers using WinDbg and C •Participated in designing and developing test utilities for upcoming graphics ASIC (with MFC) •Maintained driver test automation lab; performed WHQL tests and general driver testing on ATI integrated chipsets•Resolved general hardware issues for software teams; worked with hardware team to resolve stability issues for new integrated chipset motherboards

•Developed an indoor wireless system design automation tool in VBA in three months. Tool simplifies design and saves design time by more than 50% and was used on most large scale projects by RF engineers •Designed indoor wireless communication systems under the supervision from the engineering director and senior RF engineer. Systems designed: UHF radio, 800MHz Public Safety, iDEN, 1900MHz CDMA and GSM networks •Performed on-site wireless signal integrity testing with spectrum analyzers •Prepared project bid packages and installation packages for contractors. Interacted with project manager to solve engineering issues in the field