Jonathan Robinson Email & Phone Number

Portland, OR, US

Portland, Oregon, United States

• Essential, Performance, and Infrastructure Product Architect responsible for defining processor subsystem and SoC product solutions for various market segments.Responsibilities:
• Created and defined the architecture of SiFive’s next generation Essential processor product line providing in-order CPU solutions for extremely area and power sensitive micro controller applications, as well as the.
• Responsible for vertical SoC architecture strategy where trends are identified in a market segment and innovation is driven into the product line. Worked alongside the product architecture team to define and implement.
• Defined hardware and software strategies for large heterogeneous systems with multi-level coherence and mixed-criticality constraints. Involved partitioning workloads into properly sized compute complexes, identifying.
• Provided microarchitectural definitions and specifications for core complex interconnects, clocking, reset and power management systems. Worked with architecture and design to implement these systems as part of our.

• Data Center Group: SoC architect tasked to the Ethernet Product Group working on a new line of Infrastructure accelerators designed to revolutionize the data center platform architecture.Responsibilities:
• Responsible for architecture of server-class ARM systems including management processor, fabrics, and multi-cluster server cores. Worked closely with a key cloud customer to capture requirements, find the correct.
• Technical owner of various aspects of our integrated management solution such as the root of trust processor, and key consultant on aspects such as clocking, boot, and security.
• Involved in pathfinding efforts for the future of the infrastructure Ethernet product architecture. This involves identifying future CPU choices, multi-die strategies, coherency structures, and cache usage and structure.
• Contributor in corporate strategy regarding future CPU ISA choices for Ethernet offload products and how they might be integrated into Intel ecosystems. Provided input on multiple executive level strategy discussions.
• Responsible for developing technologies that redefine the way in which our XEON server CPUs are booted in the data center. Involved working closely with our FPGA and platform groups to specify and implement a solution.

Portland, Oregon, United States

• SoC lead architect for multiple chipset and CPU projects as well as chipset integration architect covering broad architectural and design disciplines.Responsibilities:
• Lead architect for chipset product aligned with Intel’s latest mobile CPU. Responsible for grading features with engineering and driving architecture to closure. Performed diving save to integrate automotive features.
• Lead architect for a multi-core desktop CPU design. Responsible for adapting a current architecture with new features not originally intended and working with engineering to scope changes and implement.
• Owned a mobile SoC’s top-level I/O architecture, which involved resolving architectural issues as well as acting as liaison to RTL and package design. Influenced development of a standardized system for automating GPIO.
• Responsible for clock trunking and distribution architecture for mobile SoCs and their derivatives. Created power management flows for clocking control and contributed these changes to an internal standardization.
• Clocking architect for a chipset’s onboard clock hard IP. Responsible for clock generation architecture, as well as clock bring-up flows. Responsible for flow interfacing to the chipset power controller for low power.

• Worked in set-top box ASIC development as a System-on-Chip architect, IP designer, and chip-leader on ASICs ranging up to 150 million transistors. Responsibilities:
• ASIC project management for multiple set-top and gateway SoCs including resource allocation and schedule management from conception to hardware validation.
• Top-level SoC architecture and design, management of top-level testing and RTL release, and interfacing to both ASIC layout and board design groups.
• Integration and support of MIPS and ARM CPU cores in various SoCs including RTL coding and testing of bus bridges and support logic.
• First-silicon bring up of more than half a dozen successful ASICs.
• Industry contact for determining the memory roadmap for our SoCs.

Ridgeland, MS

Mixed-signal designer in an analog/mixed-signal design center. Lead small group tasked with designing, formatting, and integrating standard cell and IO libraries for all Cadence AMS centers.