System Architect and Lead Development EngineerX86 and SPARC System Development organizations:• Products include:o X7-2 and X7-2L (1U/2U Intel – Skylake, 2015-2017)o X5-2 and X5-2L (1U/2U Intel – Haswell-EP, 2012-2014)o X3-2 and X3-2L (1U/2U Intel – Sandy Bridge-EP, 2010-2012)o X6270 M2 (Sun Blade 6000 Blade, Intel – Westmere-EP, 2009-2010)o X4170 M2 and X4270 M2 (1U/2U Intel – Westmere-EP, 2009-2010)o X4170 and X4170M2 (1U/2U Intel – Nehalem-EP… Show more System Architect and Lead Development EngineerX86 and SPARC System Development organizations:• Products include:o X7-2 and X7-2L (1U/2U Intel – Skylake, 2015-2017)o X5-2 and X5-2L (1U/2U Intel – Haswell-EP, 2012-2014)o X3-2 and X3-2L (1U/2U Intel – Sandy Bridge-EP, 2010-2012)o X6270 M2 (Sun Blade 6000 Blade, Intel – Westmere-EP, 2009-2010)o X4170 M2 and X4270 M2 (1U/2U Intel – Westmere-EP, 2009-2010)o X4170 and X4170M2 (1U/2U Intel – Nehalem-EP, 2007-2009)o Sun Blade 8000 system, and CPU Blades based on AMD Opteron and Intel Xeon (2004-2007)o Sun Fire V440 (4U, 4 CPU UltraSPARC IIIi, 2001-2003)• Solicited product requirements and goals from customers and senior management, and led the engineering team to produce concepts for review by key stakeholders, ultimately resolving the product feature-set and optimal allocation of chassis volume and product cost to CPUs, Memory, I/O, Storage, Power Conversion, and Cooling.• Authored the detailed Engineering Specifications.• Led weekly multi-disciplinary Engineering Development team meetings to track development status, identify issues and set new directions as needed.• Conceived new system features and coordinated with hardware, mechanical, BIOS, and BMC firmware teams to integrate them into the product.• Coordinated Engineering Design Reviews.• Conceived and optimized the thermal telemetry and cooling control architecture used on Oracle’s 1U & 2U rack-mount servers.• Conceived, designed, and supported several 8051 microcontroller designs for SMbus and I2C custom applications, which were used across multiple generations of servers.• Engineering point-of-contact with external vendors for NVMe Flash Storage technologies.• Drove changes into the PCI-Express 4.0 specification.• Led key debug efforts and assigned debug resources throughout the full development cycle, personally specializing in issues related to PCI-Express, SAS, SATA, USB, and SMBus. Show less