Rfic Intern
Current• Optimized bias generator circuit layout with new PDK rules by reducing resistor width to 0.2um and adjusting length to maintain target resistance. Achieved a 6.3% layout area reduction, improving die area utilization and cost efficiency.• Executed AMS transient simulation for RF path continuity in the SCUD project (ASW+CPL), verifying signal path accuracy across multiple logic states for the device. • Utilized Keysight’s VNA and VSA testbenches for detailed RFIC characterization, measuring IL, ISO, IMD, harmonics, and HKP across three IC variants. Visualized and analyzed the measured data to validate the DC and RF performance of the device.