Joseph Mathis Email & Phone Number

Santa Clara, California, Us

• Drive electrical validation of CPU High Speed I/O such as Thunderbolt/USB4 testing throughout product lifecycle (Pre-Si to Post-Production) using Design For Experiment (DFx) hooks.• Generate reports for Design Of Experiments (DOE) collected and share these in with stakeholders in different internal/external to team forums.• I have worked with DDR, PCIe, typeC, Thunderbolt interfaces • Debug and drive silicon/IP issues to closure by working closely with design engineers.• Direct and train Lab Technicians to execute experiments.• Provide technical advice to Lab Technicians when troubleshooting platforms and test setup.• Generate test plans and execute against them.

Santa Clara, California, Us

• Provided lab setup for CPU (five variations) validation.• Wrote instruction on lab setup (SOP).• Tested new thermal control devices worked with thermal design team to correct thermal problems. • Coordinate and scheduled lab staff. • Thought debug methodology and problem-solving on development boards.• Perform system debug and problem root cause analysis. • Identified a flaw in the production screening process.• Performed DDR memory debug and system testing on both client and server systems

Santa Clara, California, Us

• Board and CPU validation to ensure boards were working for all Functional Validation (FV) teams.• Collaborated with board designer to confirm boards would work for the team and FV circuits were installed correctly. • Actively participated in “Power On” ensuring the boards worked for all interfaces. • Performed quality assurance analysis on board schematics and layouts.• Worked with common hardware interfaces such as UART, I2C, SPI, JTAG, DCI• Created new re-work instructions on to fix or change board or CPU behaviors. • Facilitated training of the lab technicians to increase lab productivity. • Help build “second level” debug procedure for computer boards.• DDR memory testing that lead to timing issue with a vendor’s memory module• Experience on both client and server Platforms• DDR memory validation work in memory group

Washington, Dc, Us

• Maintain and update F/A-18 Hornet radar, weapons systems, communications, and flight electronics.• Served both on land (NAS Lemoore, California) and deployed on USS Constellation (VFA 151). • Supervised AT Shop personnel (5-10) including delegation of duties, training, and shift coordination.• Obtained CDI certification• Reported to senior staff and officers about aircraft status and safety.

Programming in Fortran

Bs, Electrical Engineering

Aa, Liberal Arts