Define packaging and system manufacturing technology roadmap for future generations of products of NVM Solutions Group;Drive pathfinding programs from definition through execution;Explore feasibility of horizon technologies and furthering fundamental understanding of packaging and module assembly.Developed three technology platforms to miniature both NVM component and SSD:Fanout of Stacked Dies for NVM components;AnyPoP for SSD BGA;Hybrid Technology for SSD card.All these inventions were filed for patent application.

Lead semiconductor package design integration to meet package technology target, including package thermal/mechanical/electrical behavior, design rule, manufacturing process, quality and reliability.

Developed Intel's High G shock test modeling BKMs.Developed learnings of adhesive popcorn behavior through mechanical analysis and experiment

Postdoctoral research on Nano Wafer Level Packaging.