Principal Integration And Yield Engineer (7Nm Td)
Current- FEOL (Fin-STI-Gate-Junction-POC) characterization technical lead for 7nm FinFET advancedtechnology development, drive product yield ramp-up and performance boost projects throughclose collaboration among cross-functional teams.- Lead failure mode and root cause analysis including inline metrology, defect detection, electricaltest of health-of-line (HOL) and DOE structures, process tool/chamber variations, and functionalyield (SRAM memory, scan-chain/ATPG logic product) correlations.- Issue and communicate problem statements and high-level messages; build yield detractor grandPareto; present overall characterization work at high-level process module, characterization, andmanagement meetings.- Member of 7nm technology review committee for new process qualification and implementation.