-Determining customer requirements and proposing solutions-Creating RTL design, simulation and modelling using SystemVerilog with Synopsys VCS/Verdi and Cadence Xcelium/SimVision-Creating Perl scripts to automate the RTL design verification process and using Cadence HAL for functional verification-Performing gate-level synthesis with Synopsys Design Compiler-Completing the formal verification process: Logic Equivalence Checking (LEC) with Cadence Conformal, Code Coverage with Synopsys Verdi-Performing static timing analysis with Synopsys PrimeTime, assisted by scripting-Performing automatic test pattern generation with Synopsys TestMAX to optimize designs-Documenting design details and conducting design reviews using Microsoft Office tools (Word/Powerpoint/Excel/Visio)

-Enforced lab policies and order across Mies Campus-Handling AV and other escalated tickets regarding projector and printer issues

-Created a set of Microsoft macros using VBA to assist the IC Architecture team improve requirement traceability for specifications. -Designed and defined a new set of IC specifications using Microsoft Word, Excel and Visio.