• x86 platform schematic/layout design experiences with Intel new generation platforms for desktop products including Alder Lake, Raptor Lake Refresh, Meteor Lake, and the latest Arrow Lake. • Own project motherboard and daughter board schematics including sensitive high-speed designs such as memory data/address buses, type-c/PD, PCIe gen5/gen4 and so on. • Lead 2-gen project riser boards layout design with layout team for PCIe gen4 routing. • A good team player to smoothly work with cross-functional teams to resolve diverse issues like BIOS, layout, EC, thermal, power and RF team. • Work closely with factory members for resolving the manufacturing issues like timely correcting the BoM issues, fixing process issues (SMT/DIP), and supporting PCBA function testing at production line. • Experienced using scope and multimeter to perform standard EE validation items (power sequencing, power noise, rising/falling timing and so on) and Intel-related hardware validation tests (CITU, RMT, IOMT). • Assist hardware team to build the first RMT automatic testing environment and analyze the logs for DDR signal quality.

• Part-time test engineer- Mobile phone antenna performance test (4G)