1. Worked as a design verification engineer at Asolid for over two years since June,20222. Familiar with SystemVerilog, UVM, VCS, flash spec and Makefile3. Participated in three projects and primarily built testcases to verify flash memory controller IP and ECC IP4. Had experience using Synopsys SATA Verification IP5. Established the UVM environment for the company and applied it in ECC IP verification