Kavitha Krishna Email & Phone Number

Natick, Massachusetts, United States

Greater Boston Area

Org leader for 40+ engineers and additionally overseeing large vendor teams (60+ contract workers).Managed structural design and execution of a high-performance mission critical custom SOC program for a major customer. Worked seamlessly across internal and external organizations.Led cross-site, multi-functional teams and delivered large complex physical design over 7 billion transistors in TSMC technology for Intel Omni-Path switch and interface products. Drove technology and IP evaluations for strategic product roadmap planning to meet customer needs and landing zone requirements. Built team through hiring, mentoring, and expertise development. Integrated newly acquired teams and leveraged diverse backgrounds and skills. As the project leader, set tone for execution on tight time-to-market project schedules, partnered with program management to model and optimize schedules, and front-lined internal and external customer engagement. Set requirements and managed dependencies with adjacencies, stakeholders, and partner teams.

Greater Boston Area

Org leader for 20+ engineers. Responsibilities included planning, tracking schedules, coordinating dependencies with partners in logic, verification, test, tools and other stakeholder teams. Outcomes included successful project execution to strict deadlines and significant revenue for Intel. Led pre-silicon physical design teams to deliver complex designs in Xeon and Itanium product lines.Managed post silicon debug team driving content deployment, tester readiness, parts inventory, for post silicon power-on and debug. Required detailed planning, coordination and optimization of limited availability of parts and very expensive test equipment.

Greater Boston Area

Delivered circuit design for critical functional blocks for various Itanium processors. Built complex custom structured data path, and synthesized physical design blocks. Delivered global clock distribution, automation, simulation, and skew management.

Developed internal CAD tool in C++ for timing and logic verification of DEC Alpha server products. Modeled and characterized various VLSI building blocks using scripting (Perl) and circuit simulation (Spice).