Keerthykrishna Ramakrishnan Email & Phone Number

Sunnyvale, California, United States

Sunnyvale, California, United States

Santa Clara, California, United States

Santa Clara, California, United States

Electric Circuits

San Diego, California, United States

India

•Performed Design Rule Check (DRC) for Synopsys Compilers: 4nm,22nm and 12nm SRAM leaf cells and clusters. •Layout vs Schematic (LVS) check for the leaf cells on 4nm,22nm, 12 nm and 16nm. •Performed the extraction check and provided SPF for the leaf cells 12nm and 16nm. •Performed checks for Synopsys Compiler 12nm to provide the abstract information to the customer for the signal and power pins used for efficient place and route.•Performed Electrical Rule Check (ERC) for 12 nm.•Performed the final QA checks for the final staging of the compiler for 40nm and 12nm technology.

• Designed high speed micro-processor units with timing and power constraints.• Performed quality checks and fixed the RTL bug for the core IP.• Analyzed Data paths of the design block and improved timing by different timing synthesis like logic optimization, detailed routing etc.

Master Of Science - Ms, Electrical And Computer Engineering

8.68 Gpa

Activities and Societies: Publication: Hardware Trojan Detection with Node Reduction using Static Timing Analysis , International.