Keith Agar Email & Phone Number

Design and verification of digital FPGAs and ASICs. Versed in VHDL, Verilog, Specman E, various synthesis tools and FPGA vendor kits (Actel, Altera, Xilinx). Have experience designing with space qualifed FPGAs. Designed tests using Perl based verification environment for both a video display chip and a mixed signal audio digital mixer module. Designed and verified a public key message verification module based on ECDSA P-224 and SHA-256. Currently creating and correcting Tcl scripts for use with Cadence simulator and Synopsys synthesis tools, as well as performing RTL updates to the chip design.

Performed a large variety of ASIC design and verification work using a variety of tools and languages. A lot of work for various TI divisions (Chicago, Dallas, Houston) and for Eastman Kodak Co.

Started as development engineer in the Copy Products division. Moved over to the company's ASIC design group in 1985 and stayed there until I left the company.