I am a technical executive with 30 years of experience in highly complex and reliable systems. I am presently managing partner and customer engineering for the Datacenter accelerators (GPUs) in the platform team at AMD. I have managed organizations of engineers and researchers with backgrounds in computer architecture, analog design, ASIC design, verification, computer system design and lab bring-up / validation. I have been responsible for several simultaneous projects including budgets, resourcing, project management and execution. I have lived and worked internationally in India and China. I have managed several culturally diverse teams. I am experienced with international standards setting in the areas of Memory subsystems (JEDEC). On the technical side, I have designed microprocessors, GPUs, caches and memory subsystems in enterprise class servers. I am accomplished in digital design flow including timing closure, and static timing analysis. I have led verification teams in pre and post silicon verification in both execution and tool delivery roles. I have deep technical experience in system level engineering, including validation of hardware, firmware, and software. This includes interactions and optimizations of virtualization, operating systems and applications. Specialties: International leadership, Hardware, Server Architecture, and Protocols including PCIe, DDR, LPDDR, HBM, OpenCAPI, GenZ
Listed skills include Hardware Architecture, Computer Architecture, Debugging, Asic, and 46 others.