I am semiconductor technocrat and experienced Design Verification Engineer, I have deep experience in verification tools, methodologies, and logic design, as well as a strong understanding of OOPs. I am responsible for developing testbenches, running simulations, debugging issues, and writing test cases to validate the design. I have hands on experience on tools like Xilinx Vivado, EDA Playground, and Cadence Xcellium. I also become familiar with industry-standard verification methodologies like UVM and gain exposure to working with verification IPs and other advanced verification techniques.