Krishna A. Email & Phone Number

SoC Application Engineer, Test Engineer in a wide variety of EDA/chip-design applications. I have over the years gained experience designing, manufacturing, and testing ASICs/FPGAs through simulation, synthesis, place & route, static timing signoff, and formal verification. I've supported the development of several tools and interfaces.I also worked as a project lead in non-EDA process related issues to unify teams across platforms.Specialties: C, C++, Perl, Tcl, Verilog/VHDL, Xcelium Simulation, Verisium Debug Platform, Genus Synthesis, Innovus Place and Route, Conformal Equivalence Checker, Conformal ECO, Conformal Low Power, Cerebrus ML Driven Chip Implementation, Tempus Signoff Timing Analysis (STA).

Listed skills include Timing Closure, Timing Signoff, Physical Synthesis, Tcl, and 17 others.

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  Principal Engineer

  Cadence Design Systems, Inc

  Nov 2010 - Present - San Jose

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  Wright State University

  Electrical Engineering