I have 7 years of Pre-Si Cache Coherency verification experience at SOC, Have spent these years writing test_bench, behavioral models from scratch to leading coherency domain verification for Intel Server SOCs. Part of coherency domain verification of four successfully taped-in (in market) Intel Icelake Server SOCs. I am very much interested in config randomization optimization at SOC, creating cross domain test plan for coherent fabric verification, finding new ways to solve cross die config/stimulus dependencies, writing SV stimulus to verify fabric and agents in UVM. I have published two research paper as author related to system config optimization in simulation test bench and four as co-author related to optimizations in test bench in DTTC Intel conference.Before joining Intel, I was Intern at Cisco where I developed Web authentication and authorization test framework.I have worked as Java developer before masters from BITS Pilani (Embedded systems), Since BTech days i have been interested in writing Arduino, Raspberry-Pi microcontroller code and always try to find ways to verify something holistically with less test cases. Always believe in learning new methodology and tools to achieve product verification faster with improved quality.