Kyle Lyson Email & Phone Number

Bozeman, Mt, Us

Bozeman, Mt

Developing high linearity and low power RFICs for Military GPS receivers. Demonstrated three consecutive 1st pass Si success on RF front-end downconverters. Was responsible for design of blocks such as LNA, VGA, mixer, biasing, PPF, and output buffers. Recently submitted a 1-12GHz wideband CMOS PLL design. Shared responsibility of all top-level simulation/verification. Performed 90% of all parasitic extraction, back-annotated simulation and layout tweaks. Carried out all RF tests and composed a thorough characterization report. The downconverters were characterized by multiple channels and wideband, low noise, low power, high dynamic range characteristics. Was responsible for design reviews and business development reviews with the customer and also program kick-off meetings with various government DoD agencies.Performed design/verification on Military Read Out Integrated Circuits (ROICs). Mixed-signal design included a first pass success PLL, switched-capacitor networks, clocking, comparison and storage circuitry. Program Management of 10+ Phase I and Phase II programs overseeing engineers from senior to entry level. Prepared schedules and budgetary. Monitored program progress with Microsoft Project. Responsible for planning company-wide design tool usage and purchasing/installing of various Cadence products. Was also involved in the data management and preparation of submitted final GDS II files for fabrication.Wrote 20+ Phase I and Phase II SBIR proposals with ~50% win rate.

Worked extensively on Delta Sigma Modulators in various processess. I was responsible for the spec definition, design and simulation of the sub-circuits and the entire system.I gained significant experience designing/simulating switch-capacitor networks and transistor-level OTAs. Using the Matlab Delta Sigma Toolbox, for pre-design simulation and system definition, was a key tool and piece of my design methodology. I was also involved w/ post-layout simulation, reduction of parasitics, and layout shielding/isolation.

Worked on delta sigma ADCs and analog/mixed-signal design.

Effectively designed and performed device scaling, process migration and simulation of Bandgap, PLL, OTAs and other IC circuit blocks. Designed a high-gain, high-bandwidth folded cascode opamp to determine the capabilities of MagnaChip’s 0.18um process. Communicated with design engineers to fix circuit errors and improve layouts and schematics. Prepared design performance documentation/characterization for reference to design engineers and professional paper presentation. Set up experiments to measure drift and variation of output data on fabricated chips.

Master'S Degree, Electrical Engineering

M.S., Electrical Engineering

Activities and Societies: Member of the Honor Society and graduated w/ highest honors, IEEE member, Tau Beta Pi.Graduated w/ a 4.0 GPA..