Working on next gen low power solutions for AMD - specifically digital LDOs

Part of the configuration firmware team working on Stratix 10/Agilex FPGA. - Lead the firmware development for the Agilex 5 series mid range product.- Work with Marketing/FAEs to define new solutions to improve customer experience.- Develop low level code in C to improve overall performance of FPGA configuration and customer use cases.- Develop Python based tests for faster automation and regression testing.- Collaborate with architecture, design, and validation on new FPGA configuration features.- Enable FPGA configuration for Quad SPI , JTAG, and AVST interface.- Running Firmware on pre-silicon environment.- Utilize the googletest framework for developing unit test.- Develop Hardware Unit and System level test to isolate bugs for certain hardware IP for feature checkout.- Debugged internal and external customer issues.- Improve unit, block and system level test coverage up to 90% in new features.- Code gatekeeper in Github to ensure production firmware adhered to coding guidelines and organization policies.- Improve firmware quality by creating and developing new test cases in python and bash for the github CI / CD.- Provide technical feedback to ensure code followed coding standards through code reviews in Github- Enable Bitstream Encryption Using AES Engine

Enabled python based debug tools for the 2nd generation Intel Scalable Processors, Cascade lake.

Validated power management content on the platform Merrifield and Moorfield 22nm SOC based off the Silvermont Architecture.

Tutored students in the field of algebra, geometry,calculus, and logic ranging from 7th-14th grade. Tutored students one-on-one, and in groups.