DDR PHY IP LeadDesign, implementation, and integration of high speed, scalable, portable, custom in-house DRAM physical interface solution. Tasks include RTL design, test development (IP, top level), synthesis/STA constraints, formal verification, lint checks, signoff, firmware development, and project oversight.

DDR PHY IP Co-DesignerInitial (shuttle) implementation of custom DRAM physical interface. Tasks include interface training SM design, test and firmware development, IP and top level synthesis and STA constraints, top level integration, simulation and formal verification.SoC Diagnostic IP Owner: Continued ownership and support of diagnostic block.

SoC IntegrationBring internal/external IP releases (RTL, synthesis, simulation modules) into top level chip development environment. Responsible for running, monitoring, and debugging top level synthesis and STA regressions.SoC Diagnostic Muxing IP Co-DesignerDesign and implementation of scripted, scalable, IP and domain based, top level SoC diagnostic muxing structure; used as common solution across all teams/chips. Provided autogenerated, browser-based javascript diagnostic register configuration tool.

SoC Integration EngineerAcquaintance and development of industry understanding and technical skills. Provide assistance with tasks as needed, while training in fundamentals of professional VLSI, Unix and EDA concepts. Tasks include power-interrupt control SM design and implementation, SoC firmware register parsing tool, synthesis and STA regression monitoring and debugging.

Responsible distributing product to vendors and keeping sales and commission records for vendors.

Responsible for the upkeep of all campus printing and copying stations.Drove van for moving supplies across campus.

Learning Assistant (LA) for Physics 1 (PHYS 1110) and Physics 2 (PHYS 1120) at the University of Colorado at Boulder.Responsible for running recitation sessions along side the TA as well as hosting office hours to provide help with course material.