Project Manager
Current• Nor flash: Developing embedded 2T p- flash and stand-alone 1T n-flash.• NAND flash development• Cell/ HV/ Core device designer• Create and maintain commend files (drc/ sizing table/ lvs)• Design and draw Testkey by Virtuoso• Tape out flow, include drc errors check/ JDV check.• Work with foundries and PE/ designer to troubleshooting process/ device/ CP/ reliability issues. • Project: Pxxx foundry 0.11um embedded 2T p-flash development: Successfully developed 0.11um embedded 2T p-flash into the foundry’s logic process. Ramp up the CP1/2 yield from 0 to an average of over 80% during the pilot run in total 4 shuttles. Pass the formal qualification and release 0.11um embedded 2T p-flash planform to foundry. • Project: 45nm 1T n-flash products development in S foundry: Testkey is workable at TQV wafer. Reduced current leakage and increased cell BVDSS to nearly 6V to solve the difficult programming issue in pilot-run state by adding the additional SAS mask/ pocket imp to replace cell pocket imp. Pilot lot product function error elimination is in progress.• Project: 50nm 1T n-flash product development in X foundry: Thicken ONO and FG to solve WL leakage is due to the CG too close to AA surface. Reduce E-filed by Cell LDD profile to solve BL leakage after cycling Pass the formal qualification and successful mass production.• Project: 28nm NAND flash product development in P foundry: Evaluate specifications of RDL for suppressing bonding crack. 1st Product trial run and WAT meet target. Logic issues are under verification• Project: Automotive grade qualification successful of 0.11um embedded 2T p-flash platform in H foundry Add CLDD IMP to reduce the resistance from BL to SG that lower Vgs and increase Icell by reverse read. Enlarged SG CD+10nm and lower SG Vt by cell IMP to suppress SG leakage after the reliability test.