Ling Yang
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Ling Yang Email & Phone Number

Physical Design and Verification Engineer, focuses on SI and PI, chip, 3DIC and system level at Xilinx/AMD at AMD
Location: San Jose, California, United States 5 work roles 2 schools
2 work emails found @xilinx.com 3 phones found area 408 LinkedIn matched
✓ Verified Jul 2026 4 data sources Profile completeness 100%

Contact Signals · 2 work emails · 3 phones

Work email l****@xilinx.com
Direct phone (408) ***-****
LinkedIn Profile matched
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Current company
AMD
Role
Physical Design and Verification Engineer, focuses on SI and PI, chip, 3DIC and system level at Xilinx/AMD
Location
San Jose, California, United States
Company size
44382 employees

Who is Ling Yang? Overview

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Quick answer

Ling Yang is listed as Physical Design and Verification Engineer, focuses on SI and PI, chip, 3DIC and system level at Xilinx/AMD at AMD, a with 44382 employees, based in San Jose, California, United States. AeroLeads shows a work email signal at xilinx.com, phone signal with area code 408, and a matched LinkedIn profile for Ling Yang.

Ling Yang previously worked as Physical Design and Verification at Amd and Design Engineer at Xilinx Inc. Ling Yang holds Msee, Electrical Engineer from University Of Illinois Urbana-Champaign.

Company email context

Email format at AMD

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{first}.{last}@xilinx.com
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AeroLeads found 2 current-domain work email signals for Ling Yang. Compare company email patterns before reaching out.

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Profile bio

About Ling Yang

Physical design electrical methodology and analysis: -- 7nm,16nm, 20nm and 28nm Xilinx FPGA GT (SerDes Interface) products -- 14nm SoC physical design electrical analysis, verification and sign off -- Static and Dynamic IR, Power EM, Signal EM, In-Rush and CPM -- Early floor planning, power gate placement, decap placement and power bump estimation -- IP integration into SoC: review spec, provide guideline and sign off -- Clock distribution rule: physical rule, insertion rule, and decap rule -- RTL and gate level power analysis Signal Integrity and Power Integrity: -- System and chip level co-design and optimization -- DDR3/4, LPDDR3 system and chip SI/PI co-simulation -- System Power Delivery Network Modeling, Simulation and Optimization -- Decap (onchip, MIM caps, PKG embedded decaps) placement optimization -- Multi-GHz clock delivery jitter analysis under power supply noise -- Voltage and timing budget Best of all -- Great root understanding and common sense -- Multi desciplinary (system, analog IP and SoC) Tools: RedHawk, Totem, VoltageStorm, HSPICE, tcl, perl, make, ADS, HFSS, Q3D, SigrityEquipments: VNA, TDR, BERT, spectrum analyzer, DCA-J

Listed skills include Signal Integrity, Pcb Design, Soc, Physical Design, and 8 others.

Current workplace

Ling Yang's current company

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AMD
Amd
Physical Design and Verification Engineer, focuses on SI and PI, chip, 3DIC and system level at Xilinx/AMD
San Jose, CA, US
Website
amd.com
Employees
44382
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Company profile
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5 roles

Ling Yang work experience

A career timeline built from the work history available for this profile.

Role listed

Amd

San Jose, Ca, Us

Physical Design And Verification

Current
Amd

Santa Clara, California, Us

Feb 2022 - Present

Design Engineer

Xilinx Inc

Xilinx GT series products, including GTH, GTY --- 7nm, 16nm, 20nm and 28nm --- Monolithic DIE, SSIT (interposer), 3DIC --- Transistor Level Dynamic analysis with package and interposer, Static Power/IR/EM, Decap Analysis --- Noise analysis with DIE, Interposer and package system --- Ansys Tools (Totem, RedHawk), Voltus tools, Spice

Jul 2014 - Oct 2022

Design Engineer

Samsung Semiconductor

14nm SoC with ARM low power design power sign off, clock spec and guide line, and noise immunitiy design guide lineAdvanced on-chip decap feasibility and implementation guideline SoC system power analysis, co-analysis and optimization for board, pakcage and onchip SoC multi-GHz clock distribution under severe power supply noise (strategy, plan and implementation)

Sep 2012 - Jun 2014

Principal Si/Pi Engineer, Si/Pi Lead

Rambus Inc

San Jose, Ca, Us

Lead the SI/PI design on Rambus high speed low power I/O interface designs -- DDR3, LPDDR -- PCIe -- Wide IO interface by 3D TSV design Responsible for -- Signal Integrity sign off (modeling, simulations, system margins) -- Power integrity sign off (System power delivery, package design sign off, chip tape out signoff) In-depth knowledge -- System performance trade off -- Physical design optimization -- Simulation tools (SPICE, ADS, powerSI) -- Modeling tools (HFSS, Q3D) -- Measurement tools (VNA, TDR, RT'Scope, DCA, Jitter analysis)

May 2000 - Sep 2012
Team & coworkers

Colleagues at AMD

Other employees you can reach at amd.com. View company contacts for 44382 employees →

IS Ish Singh Ish Singh Colleague at AmdAustin, Texas Metropolitan Area, United States View → MW Mohammad Waqar Bhat Mohammad Waqar Bhat Colleague at AmdBangalore Rural, Karnataka, India View → PJ Prabhat Jain Prabhat Jain Colleague at AmdSan Francisco Bay Area, United States View → JC Josiah Clark Josiah Clark Colleague at AmdAustin, Texas, United States View → SF Stephen Frey Stephen Frey Colleague at AmdGreater Orlando, United States View → HT Hokiewan Thezeus Hokiewan Thezeus Colleague at AmdSingapore View → RB Rizwan Bhojani Rizwan Bhojani Colleague at AmdKarāchi, Sindh, Pakistan View → DD Dylan De Haas Dylan De Haas Colleague at AmdWorcester, Massachusetts, United States View → SP Sateesh P Sateesh P Colleague at AmdKurnool, Andhra Pradesh, India View → SA Shaizeen Aga Shaizeen Aga Colleague at AmdSanta Clara, California, United States View →
2 education records

Ling Yang education

Msee, Electrical Engineer

University Of Illinois Urbana-Champaign

Bachelor Of Science (Bs), Electrical, Electronics And Communications Engineering

Southeast University
FAQ

Frequently asked questions about Ling Yang

Quick answers generated from the profile data available on this page.

What company does Ling Yang work for?

Ling Yang works for AMD.

What is Ling Yang's role at AMD?

Ling Yang is listed as Physical Design and Verification Engineer, focuses on SI and PI, chip, 3DIC and system level at Xilinx/AMD at AMD.

What is Ling Yang's email address?

AeroLeads has found 2 work email signals at @xilinx.com for Ling Yang at AMD.

What is Ling Yang's phone number?

AeroLeads has found 3 phone signal(s) with area code 408 for Ling Yang at AMD.

Where is Ling Yang based?

Ling Yang is based in San Jose, California, United States while working with AMD.

What companies has Ling Yang worked for?

Ling Yang has worked for Amd, Xilinx Inc, Samsung Semiconductor, and Rambus Inc.

Who are Ling Yang's colleagues at AMD?

Ling Yang's colleagues at AMD include Ish Singh, Mohammad Waqar Bhat, Prabhat Jain, Josiah Clark, and Stephen Frey.

How can I contact Ling Yang?

You can use AeroLeads to view verified contact signals for Ling Yang at AMD, including work email, phone, and LinkedIn data when available.

What schools did Ling Yang attend?

Ling Yang holds Msee, Electrical Engineer from University Of Illinois Urbana-Champaign.

What skills is Ling Yang known for?

Ling Yang is listed with skills including Signal Integrity, Pcb Design, Soc, Physical Design, Simulation, Power Integrity, System And Chip Co Design, and Clock Jitter Analysis.

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