Long Lam Email & Phone Number

Santa Clara, California, United States

GRA for NSF Funded Project : CRII SaTC: Design Space Modeling for Logic Obfuscation to Enable System-Wide Security during IC Manufacture and Test. Performed the following tasks: 1) Developed a quantifiable system security metric measuring error rate and error severity of logic locking induced errors 2) Developed a design space exploration tool flow, utilizing Design Space Modeling with SS-ANOVA regression, to perform direct simulation on region of interest. Tools used : Python and R (for statistical modeling) 3) Developed automation script to generate Synthesizable Verilog, tcl script, and bash script. Configurable based on logic locking configuration. Tools used: Python, Vivado, ABC Syntheizer, Sypnosys DC Submitted conference paper to ISLPED 2024 ACM/IEEE International Symposium on Low Power Electronics and Design and it has been accepted.

Rochester, New York, United States

Assisted students in learning Cadence Virtuoso for schematic and layout captures. Student developed their own standard cell library using 45 nm packages. Contributed to the reworking of the lab manuals.

TA/Grader for CMPE 480 - Digital Signal ProcessingResponsible for grading students’ assignments and answering questions regarding the course materials. Also responsible to host review sessions before midterms

Rochester

Assisted weekly lab. Developed first project for this course. Which is an interactive hardware Trojan on FPGA using Python.

Held weekly office hours walking student through the process of RTL design from pen & paper design to FPGA implementation. Topics covered: VHDL Design Clock domain crossingAXI Protocol DMA Engine Image Processing (Median filtering) HW-SW codesign

Bohemia, New York, United States

-Developed firmware using VHDL and design suites such as Quartus and Lattice Diamond -Utilized scripting in Python and TeraTerm to transmit data serially to the FPGA on board using UART -Performed and Assisted Hardware verifications on several projects, using oscilloscope and logic analyzer -In charge of the generational update for several projects. Tasks including update firmware in VHDL to support new parts, created new testbench in VHDL to verify the behavior functionality, and the corresponding documentations -Created synopsis design constrain files for several FPGA to fully constrain design and ensure all timing requirements are met

Rochester, New York, United States

Grader for CMPE 260, Digital System Design II

Bachelor'S/Master'S Combined Degree (Bs/Ms), Computer Engineering, 3.97/4.00

Activities and Societies: Tau Beta Pi, IEEE @ RITMaster Thesis: Low Power Logic Locking using Design Space Modeling to Achieve System-Wide.

Education record

Activities and Societies: National Honor Society