I am an experienced Hardware Design Engineer with a successful career. Actively participated in design of validation platforms for network processors/IA processors/chip sets. Developed validation platforms for Desktop/Server environments, worked on development of Data storage concept, General Purpose validation platform to develop features for new SSDs.As lead of the validation platform developed for new SSD features development and validation, took initiative to design the board with available resources. The design met the constrained requirements of real estate though two high pin count FPGA devices are used on Full Height Half length board with other associated logic such as DDR4 interface, I2C interface, power sequence CPLD etc. The design was in 22 layers with HDI (7-8-7). Interfaced with FAB vendors for stack-up definitions, fabrication etc. BOM management was another big activity and the effort paid a lot in getting a board to the lab with zero assembly issues. The board was made available to validation teams in one week for validation of the board features. Developed first ruler SSD to use in data center storage platforms using 2.5" SSD design. The project was completed in less than 6 months and the FAB A boards were supplied to customers. As part of Data center storage concept design, designed Mid-plane for 16" dual port SSDs and 16" ruler SSD design. Resolved board bring-up issues of dual-port SSD design working with product teams & vendors, in less than one week time. PoC was successful and product was developed. Worked with ODM to bring-out a micro-server design, The design was made available for using with new silicon in record time. Took responsibility to develop 4-processor desktop validation platform using hierarchical design using Cadence EDA tools. Interfaced with Cadence team to understand about hierarchical design concepts. FAB A design worked without any issues, there was no re-spin due to hierarchical design implementation.
Listed skills include Cadence Concept Hdl/Allegro, Pcie, Requirements Analysis, Field Programmable Gate Arrays, and 5 others.