Satyanarayana Madhira Email & Phone Number

Portland, Oregon Area, Austin Tx, Tampa Fl, Seattle Wa

Knowledgeable with Hardware Design Cycle. Experienced in development of IA based validation platforms, Designed validation boards with high speed interfaces such as DDR3/DDR4/PCIe and Ethernet interfaces. Good experience in implementation of low speed interfaces such as I2C, SMBUS, SPI & RS232 interfaces. Worked on PCB designs of up to 26 layers stack-up. Latest designs include HDI design having stack up of 7-8-7. Worked with ODM on development of micro-server design using Intel's SoC. Interfaced with FAB vendors in defining the required stack-ups for the latest designs, Interfaced with assembly vendors in procurement of parts (owned BOM management), assembly of boards. Experienced in board bring-up using lab tools. Recently obtained SCRUM Master certification - Idea is to implement it in Hardware design cycle in order to achieve quality designs in right time well before the designs reach laboratory, thus saving design re-spin costs.With GE Aviation from 03/2019 Designed Missionized IO board (IO board used in flight data processing units). MIO board is a critical subsystem that interfaces with Flight connector on one end and processing units on other end of the board. The board logic uses high pin count FPGAs. The design includes analysis of requirements (using DOORS database system), creation of Hardware Design Document (HDD), Schematics generation, conducing reviews, BOM creation, creation of routing rules, working with layout team to get layout done, release of the design to FAB vendor, Test plan preparation, board power-on. Got an opportunity to work on MIL STD interfaces such as M1553, M1394, ARINC-429 in addition to Ethernet interfaces. The board is expected to be in lab for power on tests.

Portland, Oregon Area

A dedicated and motivated self-starter with experience as a Senior Hardware Design Engineer in the area of SSD Path finding studies such as Ruler computational unit (accelerator), FPGA validation platform for development and validation of future SSD features, Data Storage system for datacenters (a proof of concept), Compute Node design for micro-server application, IA processors/chipsets validation platforms design, Custom PCBs Design such as PCIe lane bi-furcation boards and Platform Enabling Tools (Interposers) for use on validation platforms. Expert in the use of Logic Analyzers, Pattern Signal Generators and Digital Oscilloscopes. Knowledgeable in the area of Hardware Design Cycle. Proven ability to take on new assignments and follow through to completion.